基于FPGA的Turbo码快速实现算法  

Fast Implementation Encoder of Turbo Codes based on FPGA

作　　者：朱胜利 ZHU Shengli(No.10 Institute of CETC,Chengdu Sichuan 610036,China)

机构地区：[1]中国电子科技集团公司第十研究所,四川成都610036

出　　处：《通信技术》2021年第10期2326-2333,共8页Communications Technology

摘　　要：针对常用Turbo码,提出了一种资源消耗少、实用性强的基于FPGA的快速编码方法。编码器实现时,使用ROM表存储对应的交织关系以确定延迟,从而便于两路数据序列同时编码。在每一帧信息序列后添加“1”,使得两路卷积编码器同时归零。将编码输出的使能隔断,使得特定码率Turbo码的产生时序更易于控制,便于后续并串转换模块的处理。利用ISE软件和XC7VX690T芯片对编码器进行功能及性能验证,结果说明该方法结构简单,易于实现,硬件资源消耗少,适用于高低速数据传输中,具有良好的工程实践价值。Aiming at the commonly used Turbo codes,a fast and easy coding architecture based on FPGA with low resource consumption and strong practicability is proposed.When the encoder is implemented,the ROM table is used to store the corresponding interleaving relationship to determine the delay,so as to facilitate the alignment of two data sequences.Adding“1”s behind every frame information sequence to make two convolutional encoders return to zero at the same time.Isolating the enable of the code output makes the generation timing of the Turbo code of a specific code rate easier to be controlled,which is convenient for the subsequent parallel-serial conversion processing.The ISE software and the XC7VX690T chip are used to verify the function and performance of the encoder.The results indicate that the proposed architecture has a simple structure and low hardware resource consumption,is easy to implement and is suitable for low and high speed data transmission.It has good engineering practice value.

关 键 词：TURBO码 编码 卷积码 硬件实现 

分 类 号：TN911[电子电信—通信与信息系统]