基于国产FPGA的网络平台跨时钟域设计方法  

Design Method of Clock Domain Crossing for Network Platform based on Domestic FPGA

作　　者：贾永兴 杨宏[1] 刘文慧[1] 陈明 滕杰 JIA Yongxing;YANG Hong;LIU Wenhui;CHEN Ming;TENG Jie(No.30 Institute of CETC,Chengdu Sichuan 610041,China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《通信技术》2021年第10期2447-2450,共4页Communications Technology

摘　　要：针对关键电子元器件“卡脖子”问题,采用国产FPGA设计了网络平台。FPGA工作频率高,功能需求复杂,外围器件多样,给FPGA设计带来了更多要求,其中跨时钟域设计问题显得尤为重要。因此,结合工程实践,针对单比特控制信号和多比特并行信号分别提出了合理的跨时钟域同步方法,并给出了性能测试结果,对网络通信相关领域的FPGA设计实现具有借鉴意义。To solve the troublesome issue of the key electronic components,a network platform is designed using domestic FPGA.FPGA's high working frequency,complicated functional requirements,and diverse peripheral devices have brought more requirements to FPGA design.Among them,the clock domain crossing design is particularly more important.Therefore,combined with project practice,the reasonable clock domain crossing methods are proposed for both the control signal with single bit and parallel signal with multi-bit,and the test result is also put forward.This method has some values in the FPGA design for network communication related areas.

关 键 词：国产FPGA 网络平台 跨时钟域 同步方法 

分 类 号：TN919.4[电子电信—通信与信息系统]