一种紧凑型1024点流水线FFT处理器设计  

Design of a Compact 1024-point Pipelined FFT Processor

作　　者：于建[1] 霍永华[2] 焦利彬[2] 杨杨[3] YU Jian;HUO Yonghua;JIAO Libin;YANG Yang(College of Physics and Electronics,Hebei Normal University for Nationalities,Chengde 067000,China;The 54th Research Institute of CETC,Shijiazhuang 050081,China;Beijing University of Posts and Telecommunications,Beijing 100876,China)

机构地区：[1]河北民族师范学院物理与电子工程学院,河北承德067000 [2]中国电子科技集团公司第五十四研究所,河北石家庄050081 [3]北京邮电大学,北京100876

出　　处：《无线电工程》2021年第11期1326-1334,共9页Radio Engineering

基　　金：河北省自然科学基金项目(F2020101001);河北省留学回国人员资助项目(C20210301);河北省承德市科学技术研究与发展计划项目(202001B04);河北民族师范学院科学技术研究项目(PT2019026)。

摘　　要：设计了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的紧凑型1024点流水线架构快速傅里叶变换(Fast Fourier Transform,FFT)处理器。采用基-25 FFT算法用于减少旋转因子复数乘法运算的复杂度,硬件实现上采用了单路延迟负反馈(Single Delay Feedback,SDF)流水线架构。提出了旋转因子拆分方案,将旋转因子W^(i)_(1024)拆分为W^(1)_(1024)和W^(i)_(512),使得所有的复数乘法运算全部由正则有符号数(Canonical Signed Digit,CSD)常数乘法器来完成,无需任何只读存储器(Read Only Memory,ROM)对旋转因子常数值进行存储,大幅降低了设计所消耗的硬件成本。评估结果显示,与以往的设计方案相比,所提方案至少节约逻辑单元使用量(Logic Elements,LEs)28%,记忆体单元使用量(Memory bits,MBs)48%。A compact 1024-point pipelined FFT processor based on FPGA is designed.Radix-2^(5) FFT algorithm is adopted to reduce the calculation complexity of twiddle factors.The SDF pipelined architecture is used for hardware implementation.A scheme of twiddle factor partition is proposed,which divides twiddle factor W^(i)_(1024)into W^(1)_(1024)and W_(i)_(512).By doing this,all of the complex multiplications can be achieved by CSD constant multipliers.Furthermore,ROM for storing the constant values of twiddle factors can be removed,and as a result,the cost of hardware is significantly reduced.The evaluation result shows that the proposed scheme can reduce at least 28%LEs and 48%MBs as compared with previous schemes.

关 键 词：快速傅里叶变换 旋转因子 CSD常数乘法器 流水线架构 处理器 

分 类 号：TN47[电子电信—微电子学与固体电子学]