三维垂直集成器件与工艺前沿进展  

The frontier of three-dimensionally vertically integrated device and process technology

作　　者：黎明[1] LI Ming(School of Integrated Circuits,Peking University,Beijing 100871,China)

机构地区：[1]北京大学集成电路学院,北京100871

出　　处：《微纳电子与智能制造》2021年第1期4-13,共10页Micro/nano Electronics and Intelligent Manufacturing

摘　　要：集成电路技术发展进入后摩尔阶段,以三维垂直集成为特征的新兴集成工艺技术将能等效地进行微缩,从而解决衍射极限造成的平面工艺瓶颈与集成度增长需求之间的矛盾。在三维垂直集成工艺架构下,材料基础、器件结构、芯片设计都将面临诸多的新挑战和新机遇。介绍当前三维垂直集成器件与工艺的前沿进展情况以及存在的挑战。Integrated circuit technology has entered post-Moore era in which stage the emerging process technology featuring threedimensional vertical integration will play the key role in effective scaling-down and solving the contradiction between planar resolution bottleneck induced by diffraction limit and the requirement for density increasing.With the process platform of threedimensional vertical integration,the fundamental materials,device structures and design technologies will face many emerging challenges and also the opportunities.In this review,we will summarize the frontier development and existing challenges in device and process technologies for three-dimensional vertical integration.

关 键 词：摩尔时代 三维垂直集成 器件 工艺 

分 类 号：TN47[电子电信—微电子学与固体电子学]