一种基于串行蝶形单元的快速傅里叶变换硬件设计  

Fast Fourier Transform Architecture Based on Serial Butterfly Unit

作　　者：梁煜 孙文超 张为 Liang Yu;Sun Wenchao;Zhang Wei(School of Microelectronics,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学微电子学院,天津300072

出　　处：《南开大学学报（自然科学版）》2021年第5期48-52,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：国家自然科学基金(61474080)。

摘　　要：利用串行蝶形单元,设计出一种使用更少的蝶形单元、旋转因子乘法器和存储单元的快速傅里叶变换结构.并且结合基22算法的特点,与基2算法的串行蝶形单元快速傅里叶变换相比,进一步减少了硬件资源的使用,缩短了关键路径.设计的16点快速傅里叶变换在XilinxVirtex-4上所需的slice数量与其他构架相比减少了5%,工作频率提高3%.在XilinxVirtex-5上所需LUTs数量减少9%.没有使用BRAM和DSP48,节约了硬件资源.此结构实现了高效率处理快速傅里叶变换,并可以通过增加处理单元级数扩展处理点数.To solve the problem of high hardware resource cost and low hardware efficiency in serial pipeline architecture,a serial butterfly unit and a fast Fourier transform(FFT)architecture are proposed,which used less butterfly unit,rotators and memory in theory.Compared with the architecture of radix 2,this architecture takes advantage of the radix 22 algorithm’s feature,reducing the usage of hardware resource and shortening the critical path.Compared to other architectures,the proposed 16-point FFT architecture’s slice count reduces by ~8%,while the frequency rises by ~3% in Xilinx Virtex-4 FPGAs,and it reduces 9% less LUT count in the Xilinx Virtex-5 FPGAs.In addition,the synthesis result shows that it does not use the BRAM and DSP48,so it can reduce the cost of hardware sharply.The proposed architecture implements high efficient FFT and it can process bigger point FFT by adding the processing element.

关 键 词：快速傅里叶变换 串行蝶形单元 基22算法 

分 类 号：TN47[电子电信—微电子学与固体电子学]