一种降低3-D VRRAM热串扰的并行输入重编码电路  

A parallel input re-encoding circuit to reduce 3-D VRRAM thermal crosstalk effects

作　　者：陈之晟 张锋 CHEN Zhisheng;ZHANG Feng(Key Laboratory of Microelectronics Device and Integrated Technology,Institute of Microelectronics of the Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所微电子器件与集成技术重点实验室,北京100029 [2]中国科学院大学,北京100049

出　　处：《微电子学与计算机》2021年第11期95-100,共6页Microelectronics & Computer

基　　金：国家自然科学基金项目(61720106013);国家重点研究计划(2018YFB0407500);中国科学院战略重点研究项目(XDB44000000)。

摘　　要：3-D VRRAM(Vertical Resistive Random Access Memory)是一种用来降低阻变式存储器单元成本的新型架构.目前对3-D VRRAM阵列的性能评估主要集中于对写入和读取裕度的分析上.然而3-D VRRAM中的中的热串扰效应也是一个值得关注的问题,过高的热串扰会明显降低阵列中存储单元的可靠性.本文提出了一种并行输入重编码电路,通过对输入数据进行重新编码来降低大规模并行写入所引起的热串扰效应.实验结果表明,当并行写入阵列大小为4×4、4×8以及8×8时,使用本文提出的输入重编码电路可以分别降低21.8%、23.9%和12.2%的热串扰效应.此外,使用本文提出的写入重编码仅仅增加了3%的写入延时以及0.07%的额外面积.3-D Vertical Resistive Random Access Memory(VRRAM)is a new architecture widely studied to reduce the cost of resistive random access memory cells.The current performance evaluation of 3-D VRRAM arrays mainly focuses on the analysis of write and read margins.However,the thermal crosstalk effect in 3-D VRRAM is also a problem worthy of attention.Excessive thermal crosstalk will significantly reduce the reliability of memory cells in the array.This paper proposes a parallel write re-encoding circuit to reduce the thermal crosstalk effect caused by massive parallel writes by re-encoding the input data.The experimental results show that when the parallel write array size is 4×4,4×8,and 8×8,the input re-encoding circuit proposed in this paper can reduce the thermal crosstalk effect by 21.8%,23.9%,and 12.2%,respectively.Besides,using the write re-encoding proposed in this paper will only increase the write latency by 3%and the additional area of 0.07%.

关 键 词：3-D VRRAM 热串扰 并行写入 重编码电路 

分 类 号：TN710[电子电信—电路与系统]