基于R-HBT模型的三值CMOS忆阻混合型D触发器  

Ternary CMOS memristor hybrid D flip-flop based on R-HBT model

作　　者：韩琪 王旭亮 吴巧 罗文瑶 林弥[1] HAN Qi;WANG Xuliang;WU Qiao;LUO Wenyao;LIN Mi(School of Electronic Information,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2021年第6期1-5,共5页Journal of Hangzhou Dianzi University：Natural Sciences

摘　　要：研究多值忆阻逻辑电路,采用三值忆阻逻辑运算单元,设计了三值CMOS忆阻混合型D锁存器,该三值忆阻逻辑运算单元以CMOS和电阻异质结双极性晶体管(Resistor-Heterojunction Bipolar Transistor,R-HBT)负阻型忆阻器等效模型为核心,构成的三值CMOS忆阻混合型D锁存器包括4个三值忆阻与非单元和1个三值忆阻反相器,结构简单。在忆阻D锁存器的基础上,设计了上边沿触发的三值CMOS忆阻混合型D触发器,该D触发器为主从型结构。PSPICE仿真结果符合三值D触发器的逻辑功能,验证了设计的正确性。A ternary CMOS hybrid memristor D latch is proposed by using ternary memristor logic operation units.The ternary memristor logic operation unit is composed of CMOS and Resistor-Heterojunction Bipolar Transistor(R-HBT)negative resistance memristor.The ternary CMOS memristor hybrid D-latch consists of 4 ternary memristor NAND units and 1 ternary memristor inverter.A ternary CMOS memristor hybrid D flip-flop is designed based on the memristor D-latch,the D flip-flop owns the master-slave structure and is rising edge-triggered.The PSpice simulation results accord with the ternary D-flip-flop logic,which verifies the correctness of the design.

关 键 词：忆阻器 CMOS混合型 多值逻辑 D触发器 

分 类 号：TN402[电子电信—微电子学与固体电子学]