基于SoPC的改进DDFS设计与实现  

Design and Implementation of Improved Direct Digital Frequency Synthesizer Based on SoPC

作　　者：张恒康 陈明[1,2] 徐畅 谌辰睿 吴正平 ZHANG Hengkang;CHEN Ming;XU Chang;SHEN Chenrui;WU Zhengping(School of Computer and Information,China;Three Gorges University,Yichang 443000,China)

机构地区：[1]三峡大学计算机与信息学院,湖北宜昌443002 [2]湖北省水电工程智能视觉监测重点实验室,湖北宜昌443002

出　　处：《长江信息通信》2021年第11期47-51,共5页Changjiang Information & Communications

基　　金：湖北省水电工程智能视觉检测重点实验室开放基金(2020SDSJ04)。

摘　　要：针对直接数字合成器(DDFS)中杂散噪声和存储资源的问题,详细讨论了相位抖动、波形压缩分别在抑制杂散和节约存储资源上的实现方法。并利用软硬件协同设计的思想,采用相位抖动结合波形压缩的方法在ZYNQ7020 SoPC芯片上实现了一种改进的DDFS软硬件系统。改进的硬件系统输出信号的无杂散间动态范围提高了14.3dB,消耗的存储资源为传统设计的6%,软件系统可通过AXI4-Lite总线控制硬件系统实现不同的输出功能。In view of the spurious noise and storage resources in direct digital frequency synthesizer(DDFS), the implementation of phase jitter and waveform compression in reducing spurious and saving storage resources are discussed in detail. This paper utilizes the idea of software and hardware co-design to implement an improved DDFS H/S system on the ZYNQ7020 SoPC,which uses the method of phase jitter and wave compression to achieve the improvement. The test results show that the improved system’s spurious-free dynamic range is increased by 14.3 dB, while the storage resource are 6% of the traditional design, and the on-chip processor can control DDFS through the AXI4-Lite bus to achieve different output functions.

关 键 词：直接数字频率合成 相位抖动 波形压缩 无杂散间动态范围 SOPC AXI4-Lite 

分 类 号：TN741[电子电信—电路与系统]