基于快行FIR滤波器的数字下变频设计及FPGA实现  

Design of digital down converter based on fast FIR filter and its FPGA implementation

作　　者：孙星 李刚[1] 姜童[1] 孙宝华 SUN Xing;LI Gang;JIANG Tong;SUN Baohua(China Academy of Space Technology(Xi’an),Xi’an 710000,China)

机构地区：[1]中国空间技术研究院西安分院,西安710000

出　　处：《空间电子技术》2021年第5期8-13,共6页Space Electronic Technology

基　　金：装备预研基金资助项目(编号:Y19-GF-01)。

摘　　要：在雷达系统设计中,对接收的宽带回波信号直接进行中频采样,然后数字下变频实现正交解调,这样可减少系统的复杂性,提高微波遥感信号处理器的数字化程度和性能。针对高速数字下变频模块时钟速率高和硬件资源消耗大的设计难点,采用8路并行滤波方法降低时钟速率,并优化了滤波器的实现结构,在DSP48硬件资源消耗上节省大约40%。在FPGA中编程实现了8路快行滤波器的数字下变频模块,最后实验结果表明该方法在2 Gbps高速采样率下性能优异,占用硬件资源较少,具有较高的工程可行性和实用性。In order to reduce system complexity and improve the performance of signal processor,the wideband echo signal is sampled at intermediate frequency in the designation of the radar system,then digital down converter(DDC)is used to realize quadrature demodulate.Aiming at the design difficulties of the high-speed DDC module with high clock rate and large hardware consumption,this paper adopts 8-channel parallel filtering method to reduce the clock rate,and optimizes the implementation structure of the filter,which saves about 40%of DSP48 hardware resource consumption after optimization.Then the implementation of the DDC module based on 8-channel fast FIR filters in FPGA is given.Finally,the results of the experiment show that this method has excellent performance at 2 Gbps high-speed sampling rate,occupies less hardware resources,and has high engineering feasibility and practicability.

关 键 词：中频采样 数字下变频 FPGA 

分 类 号：V55[航空宇航科学与技术—人机与环境工程]