一种低开销的近似乘法器设计  

Desing of a Low-overhead Approximate Multiplier

作　　者：谢迎娟 折夏煜 褚嘉敏 王亮 蔡莉 王海滨 韩光洁 XIE Ying-juan;SHE Xia-yu;CHU Jia-min;WANG Liang;CAI Li;WANG Hai-bin;HAN Guang-jie(College of Internet of Things Engineering,Hohai University,Nanjing 211100,China;Beijing Microelectronics Technology Institute,Beijing 100076,China;Institute of Modern Physics,Chinese Academy of Sciences,Lanzhou 730000,China;Jiangsu Key Laboratory of Power Transmission&Distribution Equipment Technology,Changzhou 213000,China)

机构地区：[1]河海大学物联网工程学院,南京211100 [2]北京微电子技术研究所,北京100076 [3]中国科学院近代物理研究所,兰州730000 [4]江苏省输配电装备技术重点实验室,江苏常州213000

出　　处：《小型微型计算机系统》2021年第12期2666-2671,共6页Journal of Chinese Computer Systems

基　　金：国防科工局抗辐照应用技术创新中心重点项目(KFZC2020010401)资助;中央高校基本科研业务费项目(B200202216)资助。

摘　　要：基于精确二进制乘法器,提出了操作数裁剪方法和低开销部分积累加算法,设计了一种新型近似乘法器.对于8位和10位二进制乘法器,该近似乘法器将部分积累加步骤分别减少约42.8%和56%.另外,对比了不同乘法器的误差特性和开销.误差特性结果显示所提出的近似乘法器的平均误差距离和最大误差距离分别为3.01%和20.47%.由开销评估可知,该近似乘法器的查找表使用量和片上功耗分别为60和7.8w,相比于精确乘法器分别减少了约16.7%和46.9%.Based on the reference binary multiplier,an operand pruning method and a low-overhead accumulation algorithm of partial products are proposed in this paper,and a novel approximate multiplier is designed. For an 8-bit multiplier and a 10-bit multiplier,the proposed approximate multiplier reduces the accumulation steps of partial products by about 42. 8% and 56%,respectively. Besides,the error characteristics and overhead performance of these multipliers are compared. The results show that the average error distance and maximum error distance of the proposed approximate multiplier are 3. 01% and 20. 47%,respectively. The usage of look-up-tables and power on chip of the proposed approximate multiplier are 60 and 7. 8 w,respectively,which delivers reductions of about 16.7% and 6. 9% compared with the reference one.

关 键 词：乘法器 近似计算 部分积 低开销 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]