一种新型高速低功耗可重构流水线乘法器设计  

A new design of high-speed and low-power reconfigurable pipeline multiplier

作　　者：姚英 田心宇[2] 韩晓聪 YAO Ying;TIAN Xinyu;HAN Xiaocong(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;No.365 Institute of Northwestern Polytechnical University,Xi’an 710065,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西北工业大学第365研究所,陕西西安710065

出　　处：《电子设计工程》2022年第1期131-134,共4页Electronic Design Engineering

摘　　要：现代数字信号处理电路中常见的乘法电路随着处理信号的频率越来越快而引起功耗的大幅度增加,功耗的增加不仅造成能源浪费,而且会引起电路温度上升,影响电路正常工作。针对乘法器电路设计中要兼顾高速度和低功耗的目的,文中采用基于输入信号速率自动重构电路的方法设计了一种新型的高速高效电压可重构流水线乘法器电路。电路仿真实验表明,该电路在保证最高频率达1.8 GHz高运算速度的条件下,可有效地节省约60%的供电资源。The multiplication circuit is very common in modern digital signal processing.The multiplication circuit’s power consumption would increase greatly with the frequency of processing signal becoming faster and faster.The increase of power consumption will bring energy waste and the circuit’s temperature’s rising,and affect the normal operation of the circuit.For taking account high speed and low power in the multiplier circuit design,this article designed a new kind of high efficient reconfigurable pipeline multiplier based on the method of voltage circuit automatic reconfigurable with the input signal rate.Combined with the experiment of circuit simulation,it is proved that the circuit can save power resources of about 60%effectively under the condition of the highest frequency of 1.8 GHz.

关 键 词：高速 乘法器 流水线 可重构 

分 类 号：TN929.5[电子电信—通信与信息系统]