Implementation of PRINCE with resource-efficient structures based on FPGAs  

作　　者：Lang LI Jingya FENG Botao LIU Ying GUO Qiuping LI 

机构地区：[1]Hunan Provincial Key Laboratory of Intelligent Information Processing and Application,Hengyang Normal University,Hengyang,421002,China [2]College of Information Science and Engineering,Hunan Normal University,Changsha,410081,China [3]College of Computer Science and Technology,Hengyang Normal University,Hengyang,421002,China

出　　处：《Frontiers of Information Technology & Electronic Engineering》2021年第11期1505-1516,共12页信息与电子工程前沿（英文版）

基　　金：Project supported by the Scientific Research Fund of Hunan Provincial Education Department,China (Nos. 19A072 and 20C0268);the Science and Technology Innovation Program of Hunan Province,China (No. 2016TP1020);the Application-Oriented Special Disciplines,Double First-Class University Project of Hunan Province,China (No. Xiangjiaotong [2018] 469);the Scienceof Hengyang Normal University,China (No. 18D23);the Postgraduate Scientific Research Innovation Project of Hunan Province,China (No. CX20190980)。

摘　　要：In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components,we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight,latency-critical applications.

关 键 词：Lightweight block cipher Field-programmable gate array(FPGA) LOW-COST PRINCE Embedded security 

分 类 号：TN918.1[电子电信—通信与信息系统] TN791[电子电信—信息与通信工程]