一种高速单端多负载电路的信号完整性设计与优化  

An Optimal Design on Signal Integrity of High Speed Multi-load Bus

作　　者：戴海青[1] 徐涛[1] Dai Haiqing;Xu Tao(Nanjing Research Institute of Electronics Technology,Nanjing 210039,China)

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《信息化研究》2021年第5期23-28,44,共7页INFORMATIZATION RESEARCH

摘　　要：半导体技术的发展推动着现代数字系统的集成度和数据传输带宽的不断提升。由于系统结构、成本的限制,单端信号依然常常被考虑应用于多负载电路中。针对高速单端多负载电路,本文提出采用串联端接匹配优化经典菊花链拓扑电路的设计方法优化信号完整性,并对改进后的电路进行了反射仿真分析。最后本文通过在某一工程中实践了该方法,实测结果证明了其满足100 Mb/s高速单端多负载电路的需求,进一步证明了该方法正确性。The development of semiconductor technology promotes the continuous improvement of the integration level and data transmission bandwidth of modern digital systems. Due to system structure and cost constraints, single-ended signals are still often considered for application in multi-load circuits. Aiming at high-speed single-ended multi-load circuits, this paper proposes a design method that uses series termination matching to optimize the classic daisy chain topology circuit to optimize signal integrity, and conducts reflection simulation analysis on the improved circuit. Finally, this article mentions that the method has been practiced in a certain project, and the actual test results prove that it meets the requirements of a 100 Mb/s high-speed single-ended multi-load circuit, which further proves the correctness of the method.

关 键 词：单端 多负载 信号完整性 仿真 

分 类 号：TN702[电子电信—电路与系统]