一种10 bit电流舵型DAC的设计与仿真  

Design and simulation of a 10 bit current steering DAC

作　　者：王冠 张静[1] WANG Guan;ZHANG Jing(School of Information Science and Technology,North China University of Technology,Beijing 100144,China)

机构地区：[1]北方工业大学信息学院,北京100144

出　　处：《电子设计工程》2022年第2期170-173,179,共5页Electronic Design Engineering

摘　　要：设计了一款分辨率为10 bit、采样频率为160 MSps的数模转换器,该设计基于SMIC 55 nm1P6M标准CMOS工艺,结构为分段式电流舵型,采用模拟电源2.5 V和数字电源1.2 V双电源形式供电,具有I/Q双通道。与传统DAC结构不同的是,内部采用了一个高精度、低温漂的基准电流源代替了带隙基准电压源以及电压-电流转换电路,其温漂系数为3.1 ppm/℃。基于Q2 Random Walk电流源版图布局方法,提出了一种更为简单的中高位电流源版图交叉布局方法,有效地消除了由于梯度误差和随机误差带来的匹配性问题。DAC的版图总面积为1 050μm×800μm,总功耗为30.67 mW,SFDR=78 dB@fin=40 MHz。This paper designs a segmented current steering DAC with 10 bit resolution and 160 MSps sampling rate,the design was based on the SMIC 55 nm 1P6M CMOS standardprocess. It is under dual power supply that 2.5 V analog power and 1.2 V digital power. It has I/Q dual channel.Different from the traditional structure of DAC,a high precision and low temperature drift current reference is used instead of bandgap voltage reference and voltage to current conversion circuit,and its temperature drift coefficient is 3.1 ppm/℃.Based on Q2 random walkcurrent source layout method,a simpler layout method of medium and high level current source layout is proposed,which effectively eliminates the matching problem caused by gradient error and random error.The totalarea of this DAC is 1 050 × 800 μm;andtotalpower consumption is 30.67 mW.The measured results of post simulation shows the SFDR is 78 dB inputting 40 MHz signal.

关 键 词：电流舵 基准电流源 版图布局 低功耗 

分 类 号：TN792[电子电信—电路与系统]