符合JESD204B协议的传输层电路设计  

Design of transport layer circuit in accordance with JESD204B protocol

作　　者：陈婷婷 陆锋[1,2] 万书芹[2] 邵杰[2] CHEN Tingting;LU Feng;WAN Shuqin;SHAO Jie(College of IoT Engineering,Jiangnan University,Wuxi Jiangsu 214122,China;The 58th Research Institute,CETC,Wuxi Jiangsu 214035,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《光通信技术》2022年第1期86-90,共5页Optical Communication Technology

基　　金：国家自然科学基金项目(批准号:61704161)资助。

摘　　要：为了匹配实际应用中链路工作模式,在深入理解JESD204B协议理论的基础上,设计了一种通用的传输层电路,采用三级映射结构实现发送端、接收端传输层的组帧、解帧功能,建立Verilog编译模拟器(VCS)验证平台进行功能验证。仿真结果表明:该电路能够按照设定的链路工作模式完成采样数据与帧格式数据间的转换,实现组帧与解帧功能;基于65 nm标准工艺库综合评估,电路单通道时钟最高频率为1.25 GHz,能够达到协议支持的最高传输速度12.5 Gb/s。In order to match the link working mode in practical application,based on the in-depth understanding of JESD204B protocol theory,a general transmission layer circuit is designed,and the three-level mapping structure is used to realize the framing and deframing functions of the transmission layer at the sender and receiver.This paper establishes Verilog compilation simulator(VCS)verification platform for function verification.The simulation show that the circuit can complete the conversion between sampling data and frame format data according to the set link working mode,and realize the framing and deframing functions,and based on the comprehensive evaluation of 65 nm standard process library,the maximum frequency of single channel clock of the circuit is 1.25 GHz,which can reach the maximum transmission speed supported by the protocol of 12.5 Gb/s.

关 键 词：JESD204B协议 传输层 组帧 解帧 Verilog设计 

分 类 号：TN47[电子电信—微电子学与固体电子学]