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作 者:贾栋栋 黄海生 李鑫 惠强 JIA Dongdong;HUANG Haisheng;LI Xin;HUI Qiang(School of Electronic Engineering,Xi’an University of Post and Telecommunication,Xi’an 710121,China)
出 处:《导航定位学报》2022年第1期116-120,共5页Journal of Navigation and Positioning
基 金:国家自然科学基金——地区科学基金项目(61661049)。
摘 要:针对全球卫星导航系统(GNSS)接收机中,模数转换器(ADC)的输入信号含噪声干扰的问题,提出了一种含电平转换的全差分锁存比较器;电路由前置放大级、锁存比较级和输出缓冲级构成。采用全差分输入,提高了抗干扰、抗噪声能力;隔离管将输入电路与比较电路隔离,降低了回踢噪声;在传统锁存电路基础上,增加反馈回路和复位电路,提高了比较器的传输速度;在模拟和数字电路之间增加电平转换电路,减少数字电路功耗。该电路用于GNSS接收机中4 bit并行比较型(Flash)ADC。仿真结果表明,在中国台湾积体电路制造股份有限公司(TSMC)0.18μm互补金属氧化物半导体(CMOS)工艺下,模拟和数字电源电压分别为3.3 V和1.8 V,频率为62 MHz时,比较器输入输出延时为536.339 ps,最大失调电压为18.3 mV,平均功耗为467.4μW。Aiming at the problem that the input signal of Analog to Digital Converter(ADC)in Global Navigation Satellite System(GNSS)receiver contains noise interference,a fully differential latch comparator with level conversion is proposed.The circuit consists of preamplifier stage,latch comparator stage and output buffer stage.In order to improve the ability of antiinterference and anti noise,fully differential input is adopted;the input circuit is isolated from the comparison circuit to reduce kickback noise;the feedback circuit and reset circuit are added to the traditional latch circuit to improve the transmission speed of the comparator;the level conversion circuit is added between the analog circuit and the digital circuit to reduce the power consumption of the digital circuit.This circuit is used in 4 bit flash ADC in GNSS receiver.The simulation results show that in the Chinese Taiwan Semiconductor Manufacturing Company Limited(TSMC)0.18μm Complementary Metal-OxideSemiconductor(CMOS)process,the input and output delay of the comparator is 536.339 ps,the maximum offset voltage is 18.3 mV,and the average power consumption is 467.4μW when the analog and digital supply voltage is 3.3 V and 1.8 V,respectively,and the frequency is 62 MHz.
分 类 号:P228[天文地球—大地测量学与测量工程]
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