HDLC数据帧并行搜帧解封装模块的设计与验证  

Design and verification of HDLC data frame parallel search and decapsulation module

作　　者：钱勇 刘威[1] Qian Yong;Liu Wei(School of Physics Science and Technology,Wuhan University,Wuhan 430072,China)

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072

出　　处：《电子技术应用》2022年第1期80-83,共4页Application of Electronic Technique

摘　　要：HDLC信号链路是国际标准化组织(ISO)制定的高级数据链路的控制规程(High Level Data Link Control,HDLC)。遵循HDLC标准数据链路层规范,采用硬件描述语言Verilog HDL实现了一种基于并行结构的HDLC搜帧解封装电路,并采用System Verilog技术搭建验证平台,随机生成HDLC数据帧来验证设计正确性。使用Modelsim软件仿真波形,在仿真过程中,对于净荷区数据长度为10个字节的HDLC数据帧,解码器电路工作完成需要16个时钟周期,兼顾了处理速度和灵活性。使用QuartusII软件综合,在Altera CycloneV器件上,电路使用了8块自适应逻辑模块ALM,24个寄存器,35个引脚。The HDLC signal link is the high level data link control(HDLC)developed by the international organization for standardization(ISO).The article follows the HDLC standard data link layer specification,uses the hardware description language Verilog HDL to implement a parallel structure-based HDLC frame search and decapsulation circuit,and uses System Verilog technology to build a verification platform,and randomly generates HDLC data frames to verify the correctness of the design.Using Modelsim software to simulate waveforms,during the simulation process,for HDLC data frames with a payload area of 10 bytes,the decoder circuit requires 16 clock cycles to complete the work,taking into account processing speed and flexibility.Using QuartusⅡsoftware synthesis,on Altera CycloneV devices,the circuit uses 8 adaptive logic modules ALM,24 registers,and 35 pins.

关 键 词：HDLC协议 搜帧解封装 System Verilog MODELSIM 

分 类 号：TN702[电子电信—电路与系统]