一种全集成8位2.16 GS/s SAR ADC  

A Fully Integrated 8 bit 2.16 GS/s SAR ADC

作　　者：吴琪 张润曦[1] 石春琦[1] WU Qi;ZHANG Runxi;SHI Chunqi(Institute of Microelectronic Circuits and Systems,East China Normal University,Shanghai 200241,P.R.China)

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200241

出　　处：《微电子学》2021年第6期791-798,共8页Microelectronics

基　　金：上海市多维度重点实验室基金资助项目(18DZ2270800);华东师范大学“幸福之花”(智能+)先导研究基金资助项目(4430019311542500)。

摘　　要：设计了一种8位2.16 GS/s四通道、时间交织逐次逼近型模数转换器(TI-SAR ADC)。单通道SAR ADC采用数据环、异步时钟环的双环结构实现高速工作。采用带复位开关的动态比较器缩短量化时间,提高比较精度。结合反向单调切换时序,逐步增大共模电压,提升量化速度。基于55 nm CMOS工艺设计,后仿真结果表明,在1.2 V电源电压下,该TI-SAR ADC消耗42.6 mA电流,在奈奎斯特输入频率下,FOM值为212 fJ/(conv.step),信噪失真比(SNDR)为42.7 dB,无杂散动态范围(SFDR)为53 dB。芯片整体版图面积为3.4 mm;。A four-channel 8-bit 2.16 GS/s time-interleaved successive approximation register analog-to-digital converter(TI-SAR ADC)was designed.A dual-loop structure with an asynchronous clock loop and a data loop was explored to achieve high speed operation.A dynamic comparator with reset switches was employed to shorten the quantization time and improve the comparison accuracy.A reversed monotonic switching sequence approach was utilized to increase the input common-mode voltage and improve the quantization speed.The chip was designed in a 55 nm CMOS technology.The post-layout simulation results showed that the TI-SAR ADC achieved an FOM of 212 fJ/(conv.step),an SNDR of 42.7 dB and an SFDR of 53 dB under Nyquist input frequency,while consuming 42.6 mA current from 1.2 V power supply.The ADC occupied an area of 3.4 mm;.

关 键 词：SAR ADC 时间交织 全集成 

分 类 号：TN432[电子电信—微电子学与固体电子学]