应用于高速SAR ADC的高能效开关方案  

An Energy-Efficient Switching Scheme for High Speed SAR ADC

作　　者：张俊[1] 邓红辉[1] 桑庆华 ZHANG Jun;DENG Honghui;SANG Qinghua(Institute of VLSI Design,Hefei University of Technology,Hefei 230009,P.R.China)

机构地区：[1]合肥工业大学微电子设计研究所,合肥230009

出　　处：《微电子学》2021年第6期812-817,共6页Microelectronics

基　　金：模拟集成电路国家级重点实验室基金资助项目(6142802190506)。

摘　　要：介绍了一种应用于高速逐次逼近型模数转换器的新型高能效电容开关方案。基于2bit/cycle结构,采用两个分裂电容阵列作为数模转换器。通过单边充电操作,在减小电容阵列动态功耗和总面积的同时,提高了电容的建立速度。在最后一个量化周期中,只在电容阵列的单边引入共模电压基准,并只用一个比较器参与量化,在获得更高精度的同时,进一步降低了电容阵列的动态功耗。相比传统1bit/cycle电容开关方案,该新型电容开关方案在提升系统量化速度约2倍的同时,降低了电容阵列平均功耗83%,减小了电容总面积50%。相比其他2bit/cycle开关方案,在精度、电容总面积和功耗方面均有不同程度的改善。A novel energy-efficient capacitor switching scheme for high speed successive approximation register(SAR) analog-to-digital converters(ADC) was proposed. Based on the 2 bit/cycle architecture, two differential split capacitor arrays were employed as the digital-to-analog converter(DAC). The proposed scheme decreased the dynamic energy consumption of the capacitor arrays and the total capacitor area while it speeded up the settling of the capacitor by one-side charging operation. During the last quantization cycle, the common-voltage was introduced only to one side of the differential arrays, and just one comparator was enabled. By these, the proposed scheme got more resolution and further decreased the dynamic energy consumption. The proposed scheme achieved an 83% reduction of the average switching energy and a 50% reduction of the total capacitor area while it almost doubled the conversion speed compared with the conventional 1 bit/cycle scheme, and it got different degrees of improvement in resolution, total capacitor area and energy consumption when compared with other 2 bit/cycle schemes.

关 键 词：逐次逼近型模数转换器 两比特/周期 低功耗 电容开关方案 

分 类 号：TN792[电子电信—电路与系统]