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作 者:李晨阳 张润曦[1] 石春琦[1] LI Chenyang;ZHANG Runxi;SHI Chunqi(Institute of Microelectronic Circuits and Systems,East China Normal University,Shanghai 200241,P.R.China)
机构地区:[1]华东师范大学微电子电路与系统研究所,上海200241
出 处:《微电子学》2021年第6期842-848,共7页Microelectronics
基 金:华东师范大学“幸福之花”(智能+)先导研究基金项目(4430019311542500)。
摘 要:基于55 nm CMOS工艺,设计了一种应用于24 GHz Doppler/FMCW双模式雷达系统的模拟基带电路(ABB)。低通滤波器由两个改进型Tow-Thomas二阶节级联而成,实现了增益和带宽独立调节。采用一种基于7 bit可编程电流型数模转换器(IDAC)的两步逐次逼近型直流失调消除电路(SAR DCOC),可在Doppler模式10~600 Hz极低中频条件下,对混频器输出和基带自身直流失调进行消除。在IDAC和两级运放中混合使用BJT管,减小闪烁噪声,获得良好的低频噪声性能。后仿真结果表明,在2.5 V电源电压、模拟基带消耗电流4.9 mA下,两种模式增益范围均为6~62 dB,最大线性输入幅度(IP 1 dB)为10 dBm;62 dB增益时,Doppler模式、FMCW模式下的噪声系数分别小于42 dB、27 dB。蒙特卡罗仿真结果表明,当输入存在400 mV、200 mV直流失调时,基带输出直流失调仅为21.3 mV和16.4 mV。An analog baseband(ABB)for the 24 GHz Doppler/FMCW dual-mode radar system was designed in a 55 nm CMOS process.The low pass filter was realized by two modified Tow-Thomas bi-quad stages to adjust the gain and the bandwidth independently.In order to cancel the DC offset produced by the mixer and caused by the ABB mismatch in Doppler mode with 10~600 Hz low intermediate frequency,a two-step successive approximation register DC-offset cancellation(SAR DCOC)circuit based on a 7 bit current-programmable digital-to-analog converter(IDAC)was employed.In order to improve low frequency noise performance,the BJT devices were used in the proposed low pass filter and IDAC circuits.The post-layout simulation results showed that the proposed ABB achieved a gain from 6 to 62 dB and a maximum linear input amplitude(IP1 dB)of 10 dBm in both modes while drawing 4.9 mA from 2.5 V power supply.When the gain was 62 dB,the noise figure at Doppler and FMCW mode were lower than 42 dB and 27 dB,respectively.The Monte Carlo simulation results showed that the output DC offset were 21.3 mV and 16.4 mV while the input DC offset were 400 mV and 200 mV,respectively.
关 键 词:模拟基带 调频连续波 多普勒 可编程IDAC 逐次逼近型直流失调消除电路
分 类 号:TN957[电子电信—信号与信息处理] TN432[电子电信—信息与通信工程]
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