一种优化的MD5算法与硬件实现  

An Optimized MD5 Algorithm and Hardware Implementation

作　　者：王镇道[1] 李妮 WANG Zhendao;LI Ni(School of Physics and Electronics,Hunan University,Changsha 410082,China)

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《湖南大学学报（自然科学版）》2022年第2期106-110,共5页Journal of Hunan University:Natural Sciences

基　　金：湖南省战略性新兴产业科技攻关与重大科技成果转化项目(2017GK4008)。

摘　　要：MD5算法是应用非常广泛的一种Hash算法,在数字签名和验签中占有重要地位,算法的效率会直接影响到签名和验签的速度.本文提出一种优化的MD5算法,采用三级加法器替代四级加法器、优化循环移位操作的方式缩短MD5算法单步运算的关键路径,并用VERILOG HDL语言进行硬件实现.通过仿真和FPGA验证,结果表明该设计功能正确,硬件资源消耗少,数据吞吐量大.该设计应用于一款密码安全芯片,采用0.18μm工艺进行MPW流片,芯片面积为6 mm2.时钟频率为150 MHz,电压3.3V时,功耗约为10.7 mW.The MD5 algorithm is a widely used Hash algorithm,which occupies an important position in digital signatures and signature verification.The efficiency of the algorithm will directly affect the speed of signature and signature verification.This paper proposes an optimized MD5 algorithm,which uses a three-stage adder to replace a four-stage adder,optimizes the cyclic shift operation to shorten the critical path of the single-step operation of the MD5 algorithm,and implements the hardware in VERILOG HDL language.Through simulation and FPGA verification,the results show that the design function is correct and consumes fewer hardware resources and has a large data throughput.The design is applied to a cryptographic security chip,which uses a 0.18 μm process for MPW tape-out with a chip area of 6 mm2.When the clock frequency is 150 MHz and the voltage is 3.3 V,the power consumption is about 10.7 mW.

关 键 词：MD5算法 HASH算法 签名和验签 散列函数 

分 类 号：TN335[电子电信—物理电子学]