基于FPGA的电话计费器的设计  

Design of telephone billing device based on FPGA

作　　者：周鼎舜 覃秋荣 王颖[1] Zhou Dingshun;Qin Qiurong;Wang Ying(City College,Dalian University of technology,Dalian Liaoning,116000)

机构地区：[1]大连理工大学城市学院,辽宁大连116000

出　　处：《电子测试》2021年第23期16-18,29,共4页Electronic Test

摘　　要：现代社会离不开即时通讯工具,科学准确的计费装置的应用范围越来越广泛。电话计费器在现代化社会中具有广泛的应用价值。本文以FPGA技术位平台,以 Verilog HDL/硬件逻辑语言为基础设计了电话计费器,具有菜单模块,设置余额模块,翻译显示模块,时间模块,分频模块,调试模块,通话种类模块,通话模块。完成了模拟通话过程中的计费功能,经过验证具有实际应用价值。Modern society can not do without instant messaging tools,scientific and accurate billing device is more and more widely used.Telephone meter has a wide range of application value in modern society.Based on FPGA technology and Verilog HDL / hardware logic language,this paper designs a telephone meter,which has menu module,balance setting module,translation display module,time module,frequency division module,debugging module,call type module and call module.The billing function in the process of analog call is completed,which is verified to have practical application value.

关 键 词：FPGA Verilog HDL 电话计费器 

分 类 号：TH692[机械工程—机械制造及自动化]