基于FPGA的RISC-V CPU矩阵乘法定制指令实现  

Implementation of Customized Instruction for RISC-V CPU Based on FPGA

作　　者：邵一民 周俊[1] 秦工[1] SHAO Yimin;ZHOU Jun;QIN Gong(Jianghan University,Wuhan Hubei 430056)

机构地区：[1]江汉大学,湖北武汉430056

出　　处：《软件》2022年第1期161-164,共4页Software

摘　　要：RISC-V作为新一代开源精简指令集,具有功耗低、面积小和性能高的优点,尤其是基于FPGA实现的RISC-V CPU可以为不同应用场景进行定制优化。本文主要研究了对在FPGA中实现的RISC-VCPU添加硬件实现的自定义指令的方法,并以信号处理中常见的矩阵乘法为例,增加专用的矩阵乘法指令对重复耗时的矩阵运算进行加速,提升其在特定应用领域的整体系统性能。As a new generation open-source RISC CPU, RISC-V has many advantages such as low power dissipation, small area, high performance, etc. Especially, Realized in FPGA makes it a tailorable platform optimized for diff erent application scenarios. We researched the ways to add customized instructions in FPGA based RISC-V CPU, and realized a matrix multiplication instruction as an example to accelerate the traditional repeated and timeconsuming matrix operations that are frequently used in signal processing to improve the whole performance of the system.

关 键 词：RISC-V 自定义指令集 FPGA 

分 类 号：TP391.7[自动化与计算机技术—计算机应用技术]