基于FPGA的LZW压缩算法实现方案  

LZW Compression Algorithm Realization Based on FPGA

作　　者：韩伟坤 杨清祥 Han Weikun;Yang Qingxiang(Henan Thinker Rail Transportation Research Inc.,Zhengzhou 450001,China)

机构地区：[1]河南思维轨道交通技术研究院有限公司,郑州450001

出　　处：《单片机与嵌入式系统应用》2022年第3期66-68,73,共4页Microcontrollers & Embedded Systems

摘　　要：本文提出了一种利用FPGA实现LZW压缩算法的实现方案,描述了实现LZW算法的系统框图和控制器的控制逻辑,采用Verilog语言对核心控制单元进行模块化描述设计。在Xilinx的Artix7系列FPGA XC7A100T平台上进行仿真验证,结果表明本方案可行有效,并具有较好的移植性和可扩展性。In this paper,an implementation of the LZW compression algorithm using FPGA is proposed,the system block diagram and the control logic of the controller to implement the LZW algorithm are introduced,and the modular description design of the core control unit is used in Verilog language.Through simulation verification on Xilinx's Artix7 series FPGA XC7A100T platform,the results show that the scheme is feasible and effective with good transplantation and scalability.

关 键 词：LZW 压缩算法 FPGA FIFO RAM 

分 类 号：TN919.5[电子电信—通信与信息系统]