数据传输链路的数字量通信模块设计  

Design of Digital Communication Module of Data Transmission Link

作　　者：张岩 文丰[1] 贾兴中[1] Zhang Yan;Wen Feng;Jia Xingzhong(State Key Laboratory of Testing Technology,North University of China,Taiyuan 030051,China)

机构地区：[1]中北大学电子测试技术重点实验室,太原030051

出　　处：《单片机与嵌入式系统应用》2022年第3期78-82,87,共6页Microcontrollers & Embedded Systems

摘　　要：针对某航天器上数据采编设备在随弹发射前需要对其各个功能进行模拟验证的状况,本文设计了一种以FPGA为控制核心、RS 422和LVDS接口为数据传输链路的数字量通信模块。3路RS 422用于模拟数字量传感器的输出,一路RS 422用于模拟状态。4路异步RS 422均采用UART标准通信协议,数据接收端采用多数判决原则以保证数据传输的准确性,异步RS 422传输码率为115.2 kbps。同步RS 422采用HDLC协议,用于采编器数据的回读备份链路。LVDS传输链路使用电缆驱动器CLC001和均衡器CLC014,可以实现LVDS数据通过120 m双绞线以240 Mbps的速率零误码传输。Aiming at the need to simulate and verify various functions of the data acquisition and editing equipment on a spacecraft before launching with the missile,a digital communication module with FPGA as the control core and RS 422 and LVDS interfaces as the data transmission link is designed.Three channels of RS 422 are used to simulate the output of digital sensors,and one channel of RS 422 is used to simulate status.UART standard communication protocol is adopted in the four asynchronous RS 422 channels.The data receiver adopts the majority decision principle to ensure the accuracy of data transmission.The asynchronous RS 422 transmission rate is 115.2 kbps.Synchronous RS 422 adopts HDLC protocol,which is used as a backup link for data read-back of the data acquisition and editor.The LVDS transmission link uses the cable driver CLC001 and the equalizer CLC014 to achieve zero error transmission of LVDS data through a 120 m twisted pair cable at a rate of 240 Mbps.

关 键 词：LVDS RS 422 多数判决 零误码率 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]