基于RISC-V参数化超标量处理器的优化设计  

Optimal Design of Parameterized Superscalar Processor Based on RISC-V

作　　者：刘有耀 潘宇晨 LIU Youyao;PAN Yuchen(School of Electronic Engineering,Xi’an University of Posts&Telecommunications,Xi’an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《计算机工程与应用》2022年第5期66-74,共9页Computer Engineering and Applications

基　　金：国家自然科学基金(61834005,61874087,61772417,61802304,61634004)。

摘　　要：为解决嵌入式领域对处理器不同性能面积的需求,以及对重排序缓冲区阻塞,保留站派遣长短周期指令时导致的吞吐率不平衡及堵塞问题,设计并优化了一种简便配置的参数化流水线超标量处理器。通过定制化流水线中的分支预测,缓存与运算单元,将RISC-V指令划分5大类处理,对不同周期的执行单元采用级联与并行的混合分布方式,将充当排序缓存中的指令再派遣,达到指令暂存和分类执行的目的,使一条不定周期指令可以携带多条单周期指令提交。缓存之间以直连方式进行通信,以避免复杂的公共数据总线以降低时序损耗。实验结果表明,该处理器可以通过配置达到IPC为0.746~1.476之间的性能,平均比同类型处理器IPC提升132.4%。In order to meet the demand of embedded domain on different performance areas of the processor and to solve the issues of unbalanced throughput rate and congestion caused by reordered buffering congestion and reservation stations dispatching long-short cycle instructions,an easy-to-configure parametric pipeline superscalar processor is designed and optimized.Through predicting the branch,cache and operation unit in the customized pipeline,RISC-V instructions are divided into 5 categories of processing.For execution units in different cycles,a mixed distribution method that combines cascade and parallel is adopted.The instructions that act as to be the sort cache are re-dispatched,achieving the purposes of temporary storage of instructions and classifying executions,thereby enabling an indefinite cycle instruction to submit with carrying multiple single-cycle instructions.The communication between caches is through direct connection,for avoiding complicated common data bus,thereby reducing timing loss.It is shown in the experiment that the processor can achieve the performance with IPC between 0.746 and 1.476 through configuration,which is enhanced by 132.4%in comparison with the IPC of the same type processors.

关 键 词：流水线缓存 RISC-V指令集 超标量 参数化 指令划分 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]