一种基于EHW的分块优化电路方法  

A method of circuit blocking optimization based on EHW

作　　者：刘丽君 贺天宇 LIU Lijun;HE Tianyu(Center of Equipment Simulation Training,Shijiazhuang Campus,Army Engineering University of PLA,Shijiazhuang 050003,China;Department of Basic Course,NCO School of Artillery and Air Defense Academy,Shenyang 110000,China)

机构地区：[1]中国人民解放军陆军工程大学石家庄校区装备模拟训练中心,河北石家庄050003 [2]陆军炮兵防空兵学院士官学校基础部,辽宁沈阳110000

出　　处：《现代电子技术》2022年第6期65-68,共4页Modern Electronics Technique

基　　金：国家自然科学基金青年基金项目(61602505)。

摘　　要：针对大规模电路存在可以被优化的逻辑门,文中提出利用演化硬件(EHW)技术对大规模电路分块优化的方法。由于EHW技术只能演化小规模的电路,因此需要对大规模电路进行分解后才可以演化。首先根据逻辑门之间的连接关系,利用层次聚类的方法对大规模电路进行分解,分解后的子电路规模要适用于EHW技术;然后利用EHW技术对分解后的子电路进行演化,演化生成多种与原始子电路功能相同的电路,从中选择逻辑门最少的电路替换原始子电路,以达到优化子电路的目的;最后将优化后的子电路按照分解前的连接关系合并,得到与原始电路功能相同而逻辑门数较少的电路。实验结果表明,利用EHW技术可对大规模电路进行再优化,不仅能够降低逻辑门的数量,还可提高其安全性。As the logic gates existing in large⁃scale circuits can be optimized,a method of large⁃scale circuit block optimization using the evolvable hardware(EHW)technology is proposed.Since the EHW technology can only be used to evolve the small⁃scale circuits,the large⁃scale circuits need to be decomposed before evolution.According to the connection relationship among logic gates,the large⁃scale circuit is decomposed by means of the hierarchical clustering method,and the scales of the decomposed sub⁃circuits should be suitable for EHW technology.The EHW technology is used to evolve the decomposed sub circuits,and various circuits with the same function as the original sub circuits are generated,from which the circuits with the least logic gates are selected to replace the original sub⁃circuits to achieve optimization of the sub⁃circuits.The optimized sub⁃circuits are merged according to the connection relationship before decomposition to obtain the circuits with the same function as the original circuit and less logic gates.The experimental results show that the EHW technology can be used to optimize the large⁃scale circuit,which can not only reduce the number of logic gates,but also improve its security.

关 键 词：电路优化 EHW 电路分解 子电路演化 VLSI 子电路合并 

分 类 号：TN309.1-34[电子电信—物理电子学]