基于FPGA的集成电路芯片测试系统设计  

Design of Integrated Circuit Chip Test System Based on FPGA

作　　者：李晓东[1] LI Xiaodong(Changchun University of Technology,Jilin Changchun 130012,China)

机构地区：[1]长春工业大学,吉林长春130012

出　　处：《信息与电脑》2021年第23期125-127,共3页Information & Computer

摘　　要：针对传统系统在集成电路芯片测试应用中测试时间比较长、速度比较慢等问题,本文提出基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的集成电路芯片测试系统设计。首先,在系统硬件方面对集成电路芯片测试器进行了选型与设计,采用三线圈差动涡流电路芯片测试器对集成电路芯片进行测试,系统电路采用了10根引脚,为系统运行提供可靠电路;其次,在系统软件方面采用FPGA技术对集成电路芯片测试向量进行导入,并利用分差定位法对测试信号进行波形恢复处理;最后,利用分析算法计算集成电路芯片故障概率。经实验证明,设计系统测试时间比传统系统更短,具有较快的测试速度。Aiming at the problems of long test time and slow speed in the application of traditional system in IC chip test,this paper Based on field programmable logic gate array(field programmable gate array, FPGA). Firstly, the integrated circuit chip tester is selected and designed in terms of system hardware. The three coil Differential Eddy current circuit chip tester is used to test the integrated circuit chip. The system circuit adopts 10 pins to provide a reliable circuit for the system operation. Secondly, in the system software In the aspect of hardware, FPGA technology is used to import the IC chip test vector, and the differential positioning method is used to recover the test signal;Finally, the analysis algorithm is used to calculate the failure probability of IC chip. Experiments show that the test time of the designed system is shorter than that of the traditional system, and has faster test speed.

关 键 词：FPGA 集成电路 分差定位法 

分 类 号：TN929.5[电子电信—通信与信息系统]