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作 者:吴永超 胡锦涛 郭伟[1] 刘磊 康慧[1] 彭鹏[1] Wu Yongchao;Hu Jintao;Guo Wei;Liu Lei;Kang Hui;Peng Peng(School of Mechanical Engineering&Automation,Beihcmg University,Beijing 100191,China;State Key Laboratory of Tribology,School of Mechanical Engineering,Tsinghua University,Beijing 100084,China)
机构地区:[1]北京航空航天大学机械工程及自动化学院,北京100191 [2]清华大学机械工程学院摩擦学国家重点实验室,北京100084
出 处:《中国激光》2022年第2期12-21,共10页Chinese Journal of Lasers
基 金:国家重点研发计划(2017YFB1104900);国家自然科学基金(51975033,51775299,52075287);北京市自然科学基金(3192020)。
摘 要:集成电路(IC)芯片封装中小尺寸、细节距焊点采用的传统锡基钎料在服役过程中存在桥接、电迁移、金属间化合物等问题,在大电流、大功率密度的应用中受到限制。采用脉冲激光沉积(PLD)技术,在覆铜陶瓷(DBC)基板上图形化沉积了多孔微米银焊点,用于替代传统的钎料凸点,并将其应用于Si芯片与DBC基板的连接。结果表明:采用不锈钢作为掩模,可沉积出500μm及300μm特征尺寸的疏松多孔银焊点阵列,银焊点呈圆台形貌;在250℃温度、2 MPa压力下热压烧结10 min, Si芯片与DBC基板连接良好,连接后的银焊点边缘的孔隙率为42%左右,银焊点中心区域的孔隙率为22%;500μm和300μm特征尺寸的银焊点的连接接头的剪切强度分别为14 MPa和12 MPa;接头断裂主要发生在银焊点与芯片或DBC基板的连接界面处。Objective With the development of electronic packaging technologies towards miniaturization and integration, high requirements are put forward for the electric and heat energy transfer of chips. At present, the ball grid array(BGA) and flip-chip interconnection solder bumps in integrated circuit chips are mainly packaged with tin-based solders, which provides mechanical support and electrical interconnection between chips and substrates. However, due to the physical and chemical properties of tin balls, the problems such as bridging, electromigration, and growth of intermetallic compounds occur when the chip bumps are in service for a long time under high power and high heat flux conditions. Alternatively, the nano-metal solder pastes represented by nano silver and nano copper, can realize low-temperature bonding by virtue of their scale effect and have been attracting more and more attention in the field of electronic packaging. But the presence of organics in the nano-metal solder paste complicates the sintering process and reduces the production efficiency. Moreover, the voids caused by the insufficient decomposition of organics in the sintered joint also reduce the performance and reliability of joints. Here, we apply the pulsed laser deposition(PLD) technology, an effective method to prepare organic free silver nanostructured films, to prepare bump array with specific size and pitch. Composed of metal nanoparticles, the bumps array can be used in integrated circuit chip bonding by hot pressed sintering at low temperatures. Being a promising alternative method of traditional solder bumps, the patterned micro bump array preparation technology has important theoretical significance and engineering application value for integrated circuit chip packaging.Methods Polyimide and 304 stainless steel are employed as mask materials here. Firstly, a sandwich structure of PI/stainless steel/PI is pasted on a flat stainless steel substrate. A picosecond laser is used to fabricate the mask hole array with a total area of 1
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