基于协处理器的弹载记录仪  

Missile-borne Recorder Based on Coprocessor

作　　者：刘晓科[1] 霍丽鹏[1] LIU Xiaoke;HUO Lipeng(Xi'an Institute of Electromechanical Information Technology, Xi'an 710065, China)

机构地区：[1]西安机电信息技术研究所,陕西西安710065

出　　处：《探测与控制学报》2022年第1期86-90,共5页Journal of Detection & Control

摘　　要：针对采集炮弹发射过程中多路模拟信号存储速度受限的问题,提出基于协处理器配合双口RAM以提高数据存储速度的弹载记录仪。该记录仪采用协处理器与主控制器分别运行、协同工作的方式,主控制器完成数据的存储和上位机回读,协处理器完成待采集信号的采样和信号适配,主控制器和协处理器之间通过双端口RAM实现边采集边存储,改善了传统弹载记录仪主控制器需要分时与不同功能电路模块进行通信与控制所带来的数据传输效率低下的问题。试验验证结果表明,基于协处理器的弹载记录仪实现了3通道100 kHz模拟信号的采集以及经由双口SRAM的乒乓传输,可应用于高过载试验中弹道相关参数在较高数据传输速率情况下的采集与存储。In order to solve the problem that the storage speed of multi-channel analog signal was limited in the process of collecting projectile launching,a missile-borne recorder based on coprocessor and dual port RAM was proposed to improve data storage speed.The recorder adopted the way that the coprocessor and the main controller operate respectively and work together.The main controller completed the data storage and the upper computer readback,the coprocessor completed signal sampling and signal adaption.The dual port RAM was used between the main controller and the coprocessor to realize the acquisition and storage at the same time,which effectively improved the sampling rate of multi-channel signals.The test results showed that the missile-borne recorder based on coprocessor realized the acquisition of 3-channel/100KHz analog signal and ping-pong transmission via dual port SRAM,which could be applied to the acquisition and storage of ballistic related parameters in high overload test at high data transmission rate.

关 键 词：协处理器 双端口RAM 弹载存储 记录仪 

分 类 号：TJ414[兵器科学与技术—火炮、自动武器与弹药工程]