基于RISC-V的神经网络卷积算法的研究与优化  

Research and optimization of neural network convolution algorithm for RISC-V

作　　者：苗瑞霞 张雪兰 谭星浩 方华启 MIAO Rui-xia;ZHANG Xue-lan;TAN Xing-hao;FANG Hua-qi(College of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;Nuclei System Technology Limited Company,Wuhan 430074,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]芯来智融科技有限公司,湖北武汉430074

出　　处：《计算机工程与设计》2022年第3期668-676,共9页Computer Engineering and Design

基　　金：国家自然科学基金项目(51302215);陕西省自然科学基金项目(2018JQ6084)。

摘　　要：为加速嵌入式平台ARM CMSIS-NN上的神经网络卷积算法,提出一种面向开源RISC-V(精简指令级架构第五代)的卷积算法。采用RISC-V的P拓展指令集中特有的8位数据操作指令,优化ARM CMSIS-NN(微处理器软件接口标准)库中因为缺少DSP指令8位数据操作指令而带来的内存使用效率不高的不足。经实验仿真和下板验证,在蜂鸟E203 FPGA开发板上以16 MHz的时钟频率完成功能验证,与同等实验室实验情况下的arm-cortex-m3等设备相比,性能提升约12倍。To accelerate the neural network convolution algorithm on the embedded platform ARM CMSIS-NN,a convolution algorithm for open source RISC-V(reduced instruction level architecture fifth generation)was proposed.The special 8-bit data operation instruction of RISC-V P extension instruction set was adopted,and the inefficiency of memory usage in the ARM CMSIS-NN(microprocessor software interface standard)library was further optimized due to the lack of DSP instructions 8-bit data operation instructions.After experimental simulation and board verification,the functional verification was performed on the Hummingbird E203 FPGA development board with a clock frequency of 16 MHz.Compared with the arm-cortex-m3 and other equipment under the same laboratory experiment,the performance is improved by about 12 times.

关 键 词：ARM CMSIS-NN RISC-V 神经网络卷积算法 DSP指令集 蜂鸟E203 FPGA 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]