An integrated front-end vertical hall magnetic sensor fabricated in 0.18μm low-voltage CMOS technology  

作　　者：Zhengwu Shu Lei Jiang Xingxing Hu Yue Xu 

机构地区：[1]College of Electronic and Optical Engineering&College of Microelectronics,Nanjing University of Posts and Telecommunications,Nanjing 210023,China

出　　处：《Journal of Semiconductors》2022年第3期60-67,共8页半导体学报（英文版）

基　　金：the National Natural Science Foundation of China(Nos.61871231,62171233);the Natural Science Foundation of Jiangsu Province,China(No.BK20181390);the Key Research&Development Plan of Jiangsu Province,China(No.BE2019741);the Agricultural Science and Technology Independent Innovation Foundation of Jiangsu Province,China(No.CX(21)3062).

摘　　要：An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measure-ment.To improve the magnetic sensitivity and to obtain low offset,a fully symmetric vertical Hall device(FSVHD)has been op-timized with a minimum size design.A new four-phase spinning current modulation associated with a correlated double sampling(CDS)demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage.The vertical Hall sensor chip has been manufactured in a 0.18μm low-voltage CMOS technology and it occu-pies an area of 1.54 mm2.The experimental results show in the magnetic field range from-200 to 200 mT,the entire vertical Hall sensor performs with the linearity of 99.9%and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60μT.Meanwhile,it consumes 4.5 mW at a 3.3 V supply voltage.The proposed vertical Hall sensor is very suitable for the low-cost sys-tem-on-chip(SOC)implementation of 2D or 3D magnetic microsystems.

关 键 词：vertical Hall sensor dynamic offset cancellation 1/f noise residual offset 

分 类 号：TP212[自动化与计算机技术—检测技术与自动化装置]