Ultimate dielectric scaling of 2D transistors via van der Waals metal integration  

作　　者：Weiqi Dang Bei Zhao Chang Liu Xiangdong Yang Lingan Kong Zheyi Lu Bo Li Jia Li Hongmei Zhang Wanying Li Shun Shi Ziyue Qin Lei Liao Xidong Duan Yuan Liu 

机构地区：[1]Hunan Key Laboratory of Two-Dimensional Materials and State Key Laboratory for Chemo/Biosensing and Chemometrics,College oj Chemistry and Chemical Engineering,Hunan University,Changsha 410082,China [2]Hunan Key Laboratory of Two-Dimensional Materials,Department of Applied Physics,School of Physics and Electronics,Hunan University,Changsha 410082,China [3]Laboratory for Micro/Nano Optoelectronic Devices of Ministry of Education&Hunan Provincial Key Laboratory of Low-Dimensional Structural Physics and Devices,School of Physics and Electronics,Hunan University,Changsha 410082,China

出　　处：《Nano Research》2022年第2期1603-1608,共6页纳米研究（英文版）

基　　金：support from the National Key R&D Program of China(No.2018YFA0703700);the National Natural Science Foundation of China(Nos.51802090,61874041,51991340,and 51991341);X.D.acknowledges the support from the National Natural Science Foundation of China(No.51991343)。

摘　　要：The two-dimensional transition metal dichalcogenides(TMDs)have attracted intense interest as an atomically thin semiconductor channel for the continued transistor scaling.However,with a dangling bond free surface,it has been a key challenge to reliably integrate high-quality gate dielectrics on TMDs.In particular,the atomic layer deposition of dielectrics on TMDs typically features highly non-uniform nucleation and produces a highly rough or porous dielectric film with rich pinholes that are prone to further damage during the gate integration process.Herein we report a van der Waals(vdW)integration route towards highly reliable gate metal integration on porous dielectrics.The physical lamination process employed by the vdW integration avoids the direct deposition of metal electrodes into porous dielectrics to ensure reliable gate integration and produce low gate leakage devices.The electrical measurements demonstrate the vdW integrated MoS_(2) top gate devices exhibit substantially reduced gate leakage current that is about 3-5 orders of magnitude smaller than that with deposited metal electrodes.Furthermore,we show the vdW integration process can be used to create high performance top-gated MoS_(2) transistors with ultrathin Al_(2)O_(3) dielectrics down to 1 nm,representing the ultimate dielectric scaling for TMDs transistors.This study demonstrates that vdW integration can enable highly reliable gate integration on relatively low quality dielectrics on TMDs,and opens an interesting pathway to high-performance top-gate transistors using dangling bond free two-dimensional(2D)semiconductors.

关 键 词：van der Waals(vdW)integration dielectric scaling transfer gate MoS_(2) metal oxide semiconductor field effect transistor(MOSFET) 

分 类 号：TB3[一般工业技术—材料科学与工程]