基于混合架构的卷积神经网络算法加速研究  

Research on Acceleration of Convolutional Neural Network Algorithm Based on Hybrid Architecture

作　　者：郭子博 高瑛珂[2] 胡航天 弓铎 刘凯[1] 吴宪云 GUO Zibo;GAO Yingke;HU Hangtian;GONG Duo;LIU Kai;WU Xianyun(School of Computer Science and Technology,Xidian University,Xi’an 710071,China;Beijing Institute of Control Engineering,Beijing 100089,China;School of Communication Engineering,Xidian University,Xi’an 710071,China)

机构地区：[1]西安电子科技大学计算机科学与技术学院,西安710071 [2]北京控制工程研究所,北京100089 [3]西安电子科技大学通信工程学院,西安710071

出　　处：《计算机工程与应用》2022年第6期88-94,共7页Computer Engineering and Applications

基　　金：国家自然科学基金(61850410523)。

摘　　要：具有优越性能的卷积神经网络算法已得到广泛应用,但其参数量大、计算复杂、层间独立性高等特点也使其难以高效地部署在较低功耗和较少资源的边缘场景。为此结合该种算法的特点提出了一种基于混合架构的卷积神经网络计算加速方法,该方法选用CPU加FPGA的混合架构,对网络模型进行了压缩优化;在FPGA上通过指令控制数据流的DSP阵列结构实现了卷积计算加速;通过YOLO算法测试了该方法的加速性能,在7 000万门级FPGA上各类资源消耗低于50%且总功耗为7.36 W的情况下,吞吐率达到了120 GOPS。Convolutional neural network algorithms with superior performance have a wide range of application, but their large parameters, complex calculations, and high inter-layer independence make it difficult to efficiently deploy in edge scenarios with lower power consumption and fewer resources. For this reason, this article combines the characteristics of this algorithm and proposes a convolutional neural network computing acceleration method based on a hybrid architecture. This method uses a hybrid architecture of CPU and FPGA. The network model is compressed and optimized. Instructions are passed on the FPGA. The DSP array structure that controls the data flow realizes the acceleration of the convolution calculation. The acceleration performance of the method is tested through the YOLO algorithm. The consumption of various resources on the 70 million gate-level FPGA is less than 50% and the total power consumption is 7.36 W. In this case, the throughput rate reaches 120 GOPS.

关 键 词：现场可编程门阵列(FPGA) 卷积神经网络 DSP脉冲阵列 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]