低功耗高精度Sigma-Delta调制器的建模与设计  

Modeling and Design of Low Power and High Precision Sigma-Delta Modulator

作　　者：刘振宇 宋树祥[1] 岑明灿 蒋品群[1] 蔡超波 LIU Zhenyu;SONG Shuxiang;CEN Mingcan;JIANG Pinqun;CAI Chaobo(College of Electronic Engineering,Guangxi Normal University,Guilin Guangxi 541004,China)

机构地区：[1]广西师范大学电子工程学院,广西桂林541004

出　　处：《广西师范大学学报（自然科学版）》2022年第2期58-70,共13页Journal of Guangxi Normal University:Natural Science Edition

基　　金：国家自然科学基金(62061005);广西研究生教育创新计划项目(YCSW2021070);广西高校中青年教师科研基础能力提升项目(2020KY02028)。

摘　　要：为提升Sigma-Delta调制器精度的同时降低其功耗,本文设计一款改进型二阶单环CIFF结构Sigma-Delta调制器,通过采用运放共享技术降低由噪声整形滤波器个数引入的额外功耗;提出浮动系数迭代思想应用于调制器在MATLAB下的建模,最终确定满足精度需求的各项参数具体值,通过引入非理想因素对所得参数仿真验证满足最低性能指标后进行晶体管级电路设计。该调制器信号带宽为8 kHz,采样频率为4 MHz。电路设计使用UMC 0.11μm CMOS工艺,核心电路版图尺寸为226.8μm×187.44μm,后端仿真结果表明,当电源电压为1.2 V时,调制器总功耗为290μW。在-40~125℃,各工艺角的有效位数(ENOB)大于等于15 bits。In order to improve the accuracy of the Sigma-Delta modulator and reduce its power consumption,an improved second-order single-loop CIFF Sigma-Delta modulator is designed.The additional power consumption caused by the number of noise shaping filters is reduced by using op-amp sharing technology.The idea of floating coefficient iteration is applied to the modeling of the modulator in MATLAB,and the specific values of various parameters that meet the precision requirements are finally determined.Through the introduction of non-ideal factors,the obtained parameters are simulated and verified to meet the minimum performance index,and then the transistor level circuit is designed.The modulator has a signal bandwidth of 8 kHz and a sampling frequency of 4 MHz.The circuit design uses UMC 0.11μm CMOS process,and the core circuit layout size is 226.8μm×187.44μm.The post-simulation results show that when the power supply voltage is 1.2 V,the total power consumption of the modulator is 290μW.At-40-125℃,and the effective bits of each process Angle is more than 15 bits.

关 键 词：SIGMA-DELTA调制器 浮动系数 MATLAB建模 低功耗 高精度 语音芯片 

分 类 号：TN761[电子电信—电路与系统]