基于CMOS功耗特性的隐性脉冲触发器设计研究  

Design and Research of Recessive Pulse Trigger Based on CMOS Power Consumption

作　　者：陈微[1] 孙亚楠[1] CHEN Wei;SUN Ya-nan(College of Computer Science Technology,Beihua University,Jilin Jilin 132012,China)

机构地区：[1]北华大学计算机科学技术学院,吉林吉林132012

出　　处：《计算机仿真》2022年第1期234-237,247,共5页Computer Simulation

摘　　要：由于集成电路信号频率不断升高,尺寸不断缩小,给电路功耗控制带来严峻挑战,触发器作为主要组件,是控制功耗增加的关键要素,因此,设计了一种低功耗隐性脉冲触发器。为尽可能降低触发器功耗,针对其电路的核心功率器件CMOS进行功耗特性分析,计算各种工作状态下的功耗影响关系,给触发器设计时的功耗规避提供参考。在考虑功耗指标的同时,受电路尺寸影响,功耗与延迟产生互相博弈,于是引入TGL比较器,避免时钟控制时对MOS比较器逻辑的依赖,改善时钟控制精度,降低时间延迟。触发器工作过程包含脉冲阶段与锁存阶段,时钟控制信号会随着输入信号的变化介入或退出,从而抑制无效时钟信号,降低MOS工作状态的切换次数。通过触发器瞬态波形、功耗指标与延迟指标的仿真,验证了设计的低功耗隐性脉冲触发器逻辑控制精准,有效降低了时钟信号的冗余度,功耗指标和延迟指标均得到了显著提升。As the integrated circuit signal frequency increases and the size shrinks, it brings severe challenges to the power consumption control of the circuit. As the main component, the flip-flop is the key factor to control the increase of power consumption. Therefore, a low-power recessive pulse flip-flop is designed. In order to reduce the power consumption of the flip-flop as much as possible, the power consumption characteristics of the core power device COMS were analyzed, and the influence relationship of power consumption under various working conditions was calculated, which could provide a reference for the design of the flip-flop. Considering the power consumption index, due to the influence of circuit size, power consumption and delay play a game with each other. Therefore, a TGL comparator was introduced to avoid the dependence of MOS comparator logic in clock control, improve clock control accuracy and reduce time delay. The working process of the flip-flop includes the pulse stage and latch stage. The clock control signal will intervene or exit with the change of input signal, so as to suppress the invalid clock signal and reduce the switching times of the MOS working state. Through the simulation experiment of the transient waveform, power consumption index and delay index of the flip-flop, the control accuracy of the designed low-power recessive pulse flip-flop is verified, the redundancy of the clock signal is effectively reduced, and the power consumption index and delay index are significantly improved.

关 键 词：脉冲触发器 功耗特性 时间延迟 信号锁存 

分 类 号：TN44[电子电信—微电子学与固体电子学]