支持ⅡC接口的UHF RFID数字基带设计实现  

Design and implementation of UHF RFID digital baseband supporting ⅡC interface

作　　者：冉启鹏 王量弘 王法翔[1] RAN Qi-peng;WANG Liang-hong;WANG Fa-xiang(College of Physics and Information Engineering,Fuzhou University;Xiamen Lingyang Huaxin Technology Co.,LTD)

机构地区：[1]福州大学物理与信息工程学院 [2]厦门凌阳华芯科技有限公司

出　　处：《中国集成电路》2022年第3期54-60,共7页China lntegrated Circuit

摘　　要：针对于无源RFID数据存储的问题,提出了一种带有ⅡC接口的数字基带系统。该设计不仅完全兼容ISO 18000-6C协议,还采用了异步计数器、两级门控时钟、多时钟域等低功耗技术来满足设计的低功耗要求。利用Modelsim、QuartusⅡ软件以及DE2-115 FPGA开发板进行功能仿真与板级验证,通过ⅡC接口来读取板载存储器EEPROM,读取结果与预先存储的结果一致。采用SMIC 0.18工艺完成逻辑综合以及功耗分析,分析结果表明,电路总功耗为14.8μW,总面积为0.12mm^(2),满足设计需求。Aiming at the problem of passive RFID data storage, a digital baseband system with ⅡC interface is proposed. The design is not only fully compatible with ISO 18000-6 c protocol, but also uses low-power technologies such as asynchronous counter, two-stage gated clock and multi clock domain to meet the low-power requirements of the design. Modelsim, Quartus Ⅱ software and DE2-115 FPGA development board are used for functional simulation and board level verification. The EEPROM is read through ⅡC interface, and the read results are consistent with the pre-stored results. SMIC 0.18 process is used to complete logic synthesis and power analysis. The analysis results show that the total power consumption of the circuit is 14.8μW. The total area is 0.13 mm2, meeting the design requirements.

关 键 词：RFID 低功耗 ⅡC接口 FPGA 

分 类 号：TP391.44[自动化与计算机技术—计算机应用技术] TP333[自动化与计算机技术—计算机科学与技术]