用于硅像素探测器读出系统的流水线ADC设计  

Design of pipeline ADC for silicon pixel dector readout system

作　　者：黄芳芳 杨苹 高超嵩 孙向明 刘军 HUANG Fangfang;YANG Ping;GAO Chaosong;SUN Xiangming;LIU Jun(Key Laboratory of Quark and Lepton Physics of Ministry of Education,College of Physical Science&Technology,Central China Normal University,Wuhan 430079,China)

机构地区：[1]华中师范大学物理科学与技术学院夸克与轻子物理教育部重点实验室,湖北武汉430079

出　　处：《电子设计工程》2022年第6期1-5,共5页Electronic Design Engineering

基　　金：国家自然科学基金(11927901)。

摘　　要：设计了一款用于硅像素探测器读出系统的13 bit、20 MS/s流水线ADC芯片。该芯片的核心模块主要包括乘法数模单元(MDAC)、全差分跨导运算放大器(OTA)、动态锁存器、双相非交叠时钟产生电路等,并采用130 nm CMOS商业标准工艺完成了电路设计与仿真。后仿真结果表明,该ADC性能指标满足项目需求:工作电压为3.3 V,单端输入动态范围为-1~1 V,ENOB约为10.48 bits,SFDR为74.4 dB,SNDR为64.9 dB,SNR为65.1 dB,THD为78.3 dB,总功耗约为79 mW。A 13 bit,20 MS/s pipeline ADC for silicon pixel dector readout system is designed. The core blocks of the chip mainly includes a Multiplying Digital-Analog Converter(MDAC),fully differential Operational Transconductance Amplifier(OTA),dynamic-latched-comparator、non-overlapping clock circuits,etc. Now this chip has been designed andsimulationedby using 130 nm CMOS process. The postsimulation results show that the performance of pipeline ADC is good for the project: the operation voltage is 3.3 V,the input dynamic range is-1~1 V,ENOB is 10.48 bits,SFDR is 74.4 dB,SNDR is 64.9 dB,SNR is 65.1 dB,THD is 78.3 dB,and the power consumption is about 79 mW.

关 键 词：乘法数模单元(MDAC) 全差分跨导运算放大器 流水线ADC 有效位 

分 类 号：TN432[电子电信—微电子学与固体电子学]