基于性能匹配的SoC自适应电压调节系统  

Adaptive voltage regulating system based on performance matching for SoC

作　　者：林胜楠 梁利平[1,2] LIN Shengnan;LIANG Liping(Institute of Microelectronic of Chinese Academy of Science,Beijing 100029,China;University of Chinese Academy of Science,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《电子设计工程》2022年第6期184-188,193,共6页Electronic Design Engineering

摘　　要：SoC在不同应用场景的频率不同,导致关键路径的时序余量会有较大的差异,在芯片设计阶段,为了保证芯片最坏情况下依然能够正常运行,增加了较大的电压余量,所以固定电压供电会造成不必要的功耗损失。基于最大程度节约功耗的需求,介绍了一种基于线下校准和延时链实时监测的自适应电压调节系统,实时监测电路时序,结合数字低压差线性稳压器(DLDO)自适应调节供电电压,仿真表明,在125℃、SS工艺角下,频率从700 MHz下降到300 MHz时,相比于固定电压,AVS功耗节省14.9%~64.7%。The different frequency of SoC in different application scenarios will lead to the significant difference in the timing margin of critical path. In the design stage of the chip,in order to ensure the normal operation in the worst case,a large voltage margin will be leaved,so the fixed voltage supply will cause unnecessary power loss.Based on the maximum degree of saving power consumption demand,a adaptive voltage regulation system which based on off-line calibration and delay chain real-time monitoring of sequential circuit is introduced,combined with the digital low dropout linear regulators(DLDO) adaptive adjusting the voltage. The simulation shows that in 125 ℃,SS process,700 MHz to300 MHz frequency range,compared with the fixed voltage,the power consumption of the AVS save14.9%~64.7%.

关 键 词：自适应电压调节 线下校准 延时链监测 电压余量 实时监测 数字低压差线性稳压器 

分 类 号：TN4[电子电信—微电子学与固体电子学]