基于STM32F407的FPGA动态加载设计  

Design of FPGA Dynamic Loading Based on STM32F407

作　　者：赖川 邓蕾 张显 LAI Chuan;DENG Lei;ZHANG Xian(No.30 Institute of CETC,Chengdu Sichuan 610041,China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《通信技术》2022年第3期386-393,共8页Communications Technology

摘　　要：为了实现低成本的现场可编程门阵列(Field-Programmable Gate Array,FPGA)程序加载,提出了一种基于STM32F407的FPGA动态加载系统。该系统将Vivado编译生成的二进制(binary,bin)文件,通过网络通信,采用用户数据报协议(User Datagram Protocol,UDP)报文格式,分包传输给STM32F407,并由其通过串行外设接口(Serial Peripheral Interface,SPI)写入到SPI Flash中,再控制FPGA芯片加载程序。实测结果表明:基于STM32F407的FPGA动态加载系统工作稳定、数据传输可靠,能够满足系统设计需求。In order to achieve low-cost FPGA(Field-Programmable Gate Array) program loading, this paper proposes a FPGA dynamic loading system based on stm32f407. The system passes the binary(binary, bin)files compiled and generated by Vivado through the network, and adopts the UDP(User Datagram Protocol)message format, and transmits them to the STM32F407 in sub-packages. They are written into the SPI Flash through SPI(Serial Peripheral Interface), and then controls the FPGA chip loader. The actual measurement results indicate that the FPGA dynamic loading system based on STM32F407 works stably and data transmission is reliable, which can meet the system design requirements.

关 键 词：STM32F407 现场可编程门阵列 动态加载 低成本 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]