基于RRAM双交叉阵列结构的三值存内逻辑电路设计  

Design of Ternary Logic-in-Memory Based on RRAM Dual-Crossbars

作　　者：刘维祎 孙亚男 何卫锋[1] LIU Weiyi;SUN Yanan;HE Weifeng(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《电子科技》2022年第4期8-13,共6页Electronic Science and Technology

基　　金：国家自然科学基金(61704104)。

摘　　要：在RRAM交叉阵列结构中实现逻辑运算可以较好地解决传统冯诺依曼架构中的存储墙问题。三值逻辑相比于传统的二值逻辑,具有更少的逻辑操作数目和更快的运算速度。文中提出了一种基于RRAM双交叉阵列结构的三值存内逻辑电路设计,其中三值逻辑电路的输入与输出均通过多值RRAM的阻值表示。该结构支持两种三值逻辑门和一种二值逻辑门以提升计算速度。实验结果显示,相比于传统的二值存内逻辑电路设计,三值存内逻辑电路加法器可以减少68.84%的操作步数。相比于传统的IMPLY逻辑电路设计,三值存内逻辑电路加法器可以降低33.05%的能耗。Implementing logic within RRAM crossbar is an attractive approach to overcome the memory wall in conventional Von Neumann architecture.Ternary logic can reduce the number of logic operations and enhance the computation speed compared to binary logic.In this study,a ternary logic-in-memory scheme is proposed based on the RRAM dual-crossbar structure,in which the inputs and outputs are represented by the multi-level cells of RRAMs.Two ternary logic gates and one binary logic gate are supported in the proposed structure to effectively increase the computation speed.Experimental results show that the operation steps of the ternary logic-in-memory adder are reduced by up to 68.84%,as compared with previously published binary logic-in-memory designs.The energy consumed by the ternary logic-in-memory adder is also reduced by 33.05%when compared with previously published IMPLY-based design.

关 键 词：三值存内逻辑 存储墙 阻变存储器 RRAM交叉阵列 多值单元 混合CMOS-MLC 三值加法器 碳纳米晶体管 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN99