基于FPGA的LDPC译码器的设计与实现  

Design and implementation of LDPC decoder based on FPGA

作　　者：王兰珠 李锦明 Wang Lanzhu;Li Jinming(School of Instrument and Electronics,North University of China,Taiyuan 030000,China)

机构地区：[1]中北大学仪器与电子学院,太原030000

出　　处：《电子测量技术》2022年第1期22-27,共6页Electronic Measurement Technology

摘　　要：为提高译码性能,基于CCSDS标准中应用于近地空间的(8176,7154)LDPC码,根据归一化最小和译码算法理论,设计实现了尺度因子可变的LDPC译码器。本次译码器的设计主要对校验结点量化数据进行优化处理,设计实现了尺度因子随迭代次数变化而变化,且尺度因子值以2的倍数为基数,采用右移相加代替校验结点数据与尺度因子的乘法运算,简化硬件实现。此外,增加了译码校验模块来检验经校验结点与变量结点迭代计算后的码字是否译码成功,译码成功或到达设定的最大迭代次数后将数据发出。基于FPGA设计实现了LDPC译码器,其中硬件设计中采用部分并行的译码电路,合理利用硬件资源。在信噪比为1.8、最大迭代次数为15时,通过仿真及板级验证,并对比尺度因子值为0.5、0.75及尺度因子可变时的译码结果,证明了可变尺度因子NMS译码算法可以实现译码功能且具有较好的译码性能。To improve the decoding performance,based on the(8176,7154)LDPC code applied to near-earth space in CCSDS standard,and according to the normalized minimum sum(NMS)decoding algorithm,design and implement the LDPC decoder.The design of the decoder mainly optimized the quantization data of check nodes,the scale factor changes with the number of iterations,and the scale factor value is based on the multiple of 2 and used the right shift addition to replace the multiplication of check node data and scale factor,which simplifies the hardware implementation.In addition,add a decoding verification module to test whether the codeword is successfully decoded after iterative calculation of the check node and the variable node,and the data is sent out after successful decoding or reaching the set maximum number of iterations.The LDPC decoder is designed and implemented based on FPGA.In the hardware design,used parallel decoding circuits to make rational use of hardware resources.When the signal-to-noise ratio is 1.8 and the maximum number of iterations is 15,through simulation and board-level verification,and comparing the decoding results when the scale factor value is 0.5,0.75 and the scale factor is variable,it is proved that the variable scale factor NMS decoding algorithm can realize the decoding function and has good decoding performance.

关 键 词：LDPC码 译码器 可变尺度因子 NMS译码算法 FPGA 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]