一种延迟可控的异步FIFO电路设计  

Design of a Controllable Delay Asynchronous FIFO Circuit

作　　者：陈婷婷 陆锋[1,2] 万书芹[2] 邵杰[2] CHEN Tingting;LU Feng;WAN Shuqin;SHAO Jie(College of IoT Engineering,Jiangnan University,Wuxi,Jiangsu 214122,P.R.China;The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu 214035,P.R.China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《微电子学》2022年第1期42-46,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61704161)。

摘　　要：基于传统异步FIFO延迟电路设计了一种延迟可控的异步FIFO电路。该电路在实现数据跨时钟域传输的同时增加了延迟控制模块,通过调节读指针与写指针的差值实现整数延迟的控制,通过调节读时钟与写时钟的相位差实现高精度的小数延迟控制。建立VCS验证平台,进行功能验证。结果表明,该FIFO电路实现了数据跨时钟域传输和延迟动态控制,在多芯片同时工作时可用于补偿数据源未对齐引起的输出偏斜。基于180 nm标准CMOS工艺库完成逻辑综合,读、写时钟频率分别为389 MHz、778 MHz,占用逻辑资源面积41071μm^(2)。Based on the traditional asynchronous FIFO circuits,a controllable delay asynchronous FIFO circuit structure was designed.The delay control module was added to the circuit while realizing the data transmission across clock domain.The integral delay was controlled by adjusting the difference between the read pointer and the write pointer,and the fractional delay was controlled by adjusting the phase difference between the read clock and the write clock.The VCS verification platform was established for functional verification.The results showed that data transmission across clock domain and delay dynamic control could be achieved in this FIFO circuit.The output skew caused by data source misalignment could be compensated when multichips worked at the same time.Based on a 180 nm standard CMOS process library,the read clock frequency was 389 MHz,and the write clock frequency was 778 MHz.The logic resource area was 41071μm^(2).

关 键 词：FIFO 插值率 整数延迟 小数延迟 

分 类 号：TN432[电子电信—微电子学与固体电子学]