集成电路UVM验证环境典型结构设计  

Typical Structure Design of Integrated Circuit UVM Verification Environment

作　　者：孙晓东 王治强 SUN Xiaodong;WANG Zhiqiang(School of Intelligence and Electronic Engineering, Dalian Neusoft University of Information, Dalian 116023, China)

机构地区：[1]大连东软信息学院智能与电子工程学院,辽宁大连116023

出　　处：《测试技术学报》2022年第2期135-140,共6页Journal of Test and Measurement Technology

摘　　要：UVM作为通用的验证方法学,可以利用其为待测模块DUT(Design under Test)搭建验证环境并进行验证.由于UVM是一个通用整体结构,适用于所有待测模块,在详细设计时需要一定时间考虑各组件的具体功能设计.将待测模块按照功能和类型分为总线协议、控制和算法3种类型,根据待测模块类型细化reference model和scoreboard的设计,提出典型的UVM验证环境结构.利用该UVM验证环境结构,验证工程师在整体架构下,重点考虑特殊功能部分的设计,可以缩短验证环境系统结构的设计时间.As a general verification methodology,UVM can be used to build a verification environment for DUT.Because UVM is a general structure,which is suitable for all modules to be tested,it needs a certain time to consider the specific functional design of each component in the detailed design.According to the function and type,the modules to be tested are divided into three types:bus protocol,control and algorithm.According to the types,the design of reference model and scoreboard is refined,and a typical structure of UVM verification environment is proposed.By using the structure of UVM verification environment,the verification engineer can focus on the design of special parts under the overall architecture,which can shorten the design time of the verification environment system structure.

关 键 词：UVM 验证环境 总线协议 算法模块 控制模块 

分 类 号：TN47[电子电信—微电子学与固体电子学]