基于SRT4的整数除法器设计与优化  

Design and Optimization of Integer Divider Based on SRT4

作　　者：卫祥庆 秦水介[1,2] WEI Xiangqing;QIN Shuijie(Guizhou Key Laboratory of Optoelectronic Technology and Application,Guiyang 550025,China;College of Big Data and Information Engineering,Guizhou University,Guiyang 550025,China)

机构地区：[1]贵州省光电子技术及应用重点实验室,贵阳550025 [2]贵州大学大数据与信息工程学院,贵阳550025

出　　处：《微处理机》2022年第2期1-5,共5页Microprocessors

基　　金：贵州省优秀青年科技人才项目([2019]5650);贵州省科技人才及人才团队项目(黔科合平台人才[2018]5616)。

摘　　要：为改良处理机中除法的算法表现,使用SRT-4实现对SRT-64算法的模拟,用Verilog设计并实现一个整数除法器。设计通过对数据的预处理,以SRT4算法为基础,每个周期3次迭代,等效于基数64位数的递归除法。在商的位选中加入并行中间值,对中间数据处理进行冗余计算。运算的最终延迟通过数位循环数加上一些额外的循环,用于规格化和商位的数据写回,相比SRT-16算法降低硬件的复杂度,缩短运算的时钟周期。通过在SMIC180下的工艺库完成综合仿真,得到面积和时序报告。In order to improve the performance of division algorithm in processor, SRT-4 is used to simulate SRT-64 algorithm, and Verilog is used to design and implement an integer divider. Through data preprocessing, the design is based on SRT4 algorithm, with 3 iterations per cycle, which is equivalent to the recursive division of radix 64 digits. Parallel intermediate values are added to the bit selection of quotient, and redundant calculation is carried out for intermediate data processing. The final delay of operation is used for data write-back of normalization and quotient bits by adding some extra cycles to the number of digital cycles. Compared with SRT-16 algorithm, it reduces the complexity of hardware and shortens the clock cycle of operation. Comprehensive simulation is completed in the process library under SMIC180, and the area and time series report are obtained.

关 键 词：SRT-4算法 整数除法 算法优化 迭代 综合 

分 类 号：TP332.22[自动化与计算机技术—计算机系统结构]