基于FPGA的PCIe接口逻辑设计与实现  

Design and implementation of PCIe interface logic based on FPGA

作　　者：李龙乾 方华 冯姣 李鹏[1] LI Longqian;FANG Hua;FENG Jiao;LI Peng(School of Electronic&Information Engineering,Nanjing University of Information Science&Technology,Nanjing Jiangsu 210044,China)

机构地区：[1]南京信息工程大学电子与信息工程学院,江苏南京210044

出　　处：《太赫兹科学与电子信息学报》2022年第4期385-392,共8页Journal of Terahertz Science and Electronic Information Technology

基　　金：国家自然科学基金资助项目(61501244,61501245);江苏省自然科学基金资助项目(BK20150932)。

摘　　要：为了提升高速串行计算机扩展总线标准(PCIe)总线互联设备在高速通信过程中的系统性能,减少对中央处理器(CPU)资源的占用,基于Kintex-7系列现场可编程逻辑门阵列(FPGA)平台进行总线主控式直接存储访问(DMA)设计,通过PCIe接口实现了主机设备(PC)与FPGA设备之间的高性能数据传输。同时,基于RootPort仿真平台设计DMA读写测试用例,仿真结果验证PCIe接口逻辑的正确性。通过连接上位机和配置驱动进行实际传输速率测试,结果表明,DMA写速率最高可达1620 MB/s,DMA读速率最高可达1427 MB/s,带宽最大值能够达到PCIe接口理论带宽值的84%。设计方案成本低,可靠性高,能够满足高性能、低延时的数据采集要求。The bus master Direct Memory Access(DMA)controller is implemented based on the Kintex-7 series Field Programmable Gate Array(FPGA)platform in order to improve the system performance of Peripheral Component Interconnect express(PCIe)bus interconnection devices in the process of high-speed communication and reduce the consumption of Central Processing Unit(CPU)resources.The high performance data transmission between Personal Computer(PC)and FPGA via PCIe is realized.DMA test cases are designed through the Root Port simulation platform,and the simulation results verify the correctness of the PCIe interface logic.The actual transmission rate is tested through the master computer and driver,and the experimental results show that the measured highest transfer rates are 1620 MB/s on write and 1427 MB/s on read,which reaches 84%of the theoretical maximum.The design scheme bears the advantages of low cost and high reliability,and can meet the requirements of data acquisition with high performance and low delay.

关 键 词：高速串行计算机扩展总线标准 现场可编程逻辑门阵列 直接存储访问 数据传输 

分 类 号：TP397.1[自动化与计算机技术—计算机应用技术]