自主可控的CPU与多片FPGA千兆以太网接口  

Independent and Controllable Gigabit Ethernet Interface of CPU and Multiple FPGAs

作　　者：赵晓龙 王志浩 于磊磊 ZHAO Xiao-long;WANG Zhi-hao;YU Lei-lei(Hebei Branch of China Communication System Co.,Ltd.)

机构地区：[1]中华通信系统有限责任公司河北分公司

出　　处：《中国集成电路》2022年第4期68-71,共4页China lntegrated Circuit

摘　　要：随着通信系统的国产化率要求越来越高,以太网接口的器件国产化已迫在眉睫。本文提出了一种全国产化芯片的千兆以太网接口电路,实现了一片CPU与四片FPGA之间的网络通信。文章介绍了该千兆以太网接口的系统架构,并说明了软件配置流程及硬件接口电路。With the increasing localization rate of communication system,the localization of ethernet interface devices has been imminent.This paper proposes a gigabit ethernet interface circuit with domestic chips and implements the communication of CPU and multiple FPGAs.This article introduces the system architecture of the gigabit ethernet interface,illustrates the process of software configuration and hardware interface circuit.

关 键 词：千兆以太网 国产芯片 FPGA 

分 类 号：TN402[电子电信—微电子学与固体电子学]