化学气相沉积技术在先进CMOS集成电路制造中的应用与发展  

Application and Development of Chemical Vapor Deposition Technologies in CMOS Integrated Circuit Manufacturing Process

作　　者：倪金玉 LEE ChoongHyun 何慧凯 赵毅 NI Jinyu;LEE ChoongHyun;HE Huikai;ZHAO Yi(China Nanhu Academy of Electronics and Information Technology,Jiaxing 314001,China)

机构地区：[1]中国电子科技南湖研究院,浙江嘉兴314001

出　　处：《智能物联技术》2022年第1期1-7,共7页Technology of Io T& AI

基　　金：浙江省“领雁”研发攻关计划,“面向图像应用的感存算融合芯片研究”(No.2022C01098);科技创新2030-“新一代人工智能”重大项目(批准号:2020AAA0109001);中央高校基本科研业务费专项资金资助(批准号:2020XZZX005-06)。

摘　　要：随着CMOS集成电路晶体管尺寸不断微缩及其制造工艺的日益复杂,对化学气相沉积CVD薄膜制备工艺的要求越来越高。本文主要研究了用于介质间隙填充的流CVD技术和用于SiGe选择性外延的亚常压CVD技术,重点介绍了它们的工艺原理和方法,以及薄膜材料质量及其关键影响因素。本文综述了CVD技术的特点、优势及其在先进CMOS制造工艺中的应用;面对更先进工艺应用中的挑战,分析了它们存在的问题,并讨论了可能的解决方案和应用前景。With the continuous scaling-down of CMOS integrated circuit transistor size and the increasing complexity of the manufacturing process,the requirements for the film preparation by chemical vapor deposition(CVD)are increasing.This review article mainly investigated the flowable CVD technology for dielectric gap fill and the subatmospheric pressure CVD technology for SiGe selective epitaxy,focusing on their principles and methods,as well as the quality of film materials and their key influencing factors.The article summarized the characteristics and advantages of CVD technology and their applications in advanced CMOS manufacturing processes.Facing the challenges in the application of more advanced processes,their drawbacks and research trends were analyzed,and the possible solutions and application prospects were discussed.

关 键 词：CMOS集成电路制造工艺 介质间隙填充 流化学气相沉积 选择性外延 亚常压化学气相沉积 

分 类 号：TN605[电子电信—电路与系统] TN405