FPGA与MCU自定义并行总线通信设计及实现  

Design and Implementation of Parallel Communication of Custom Bus Based on FPGA and Single-Chip Microcomputer

作　　者：戴越 张林[1] 刘广民[1] 张勇斌[1] 荆奇[1] 沈杰 Dai Yue;Zhang Lin;Liu Guangmin;Zhang Yongbin;Jing Qi;Shen Jie(Institute of Machinery Manufacturing Technology,China Academy of Engineering Physics,Mianyang Sichuan,621900)

机构地区：[1]中国工程物理研究院机械制造工艺研究所,四川绵阳621900

出　　处：《电子测试》2022年第5期9-13,共5页Electronic Test

摘　　要：在多控制器的嵌入式系统中,控制器之间可靠的数据通信决定了系统运行稳定性。本文针对FPGA与单片机的总线通信提出了自定义并行总线通信设计方法,该总线共设有40路IO线,其中8路作为控制总线用于控制数据传输,16路作为数据总线用于单片机向FPGA发送数据,另16路数据总线用于单片机从FPGA接收数据,即采用双向16位传输方案,可以满足更大范围的数据传输要求。此外,提出了适用于该总线设置的硬件电路结构及数据传输协议。最后通过实验完成了该自定义并行总线的双向通信实验测试,结果表明该自定义总线通信实时性高,通信过程稳定可靠。In a multi-controller embedded system,the reliable data communication between the controllers determines the stability of the system.This article proposes a custom parallel bus communication design method for the bus communication between FPGA and single-chip microcomputer.The bus has a total of 40 IO lines,of which 8 are used as control buses to control data transmission,and 16 are used as data buses for MCU to FPGA.Send data,and the other 16 data buses are used by the microcontroller to receive data from the FPGA,that is,a two-way 16-bit transmission scheme is adopted,which can meet a wider range of data transmission requirements.In addition,the hardware circuit structure and data transmission protocol suitable for the bus configuration are proposed.Finally,the two-way communication experiment test of the custom parallel bus is completed through experiments.The results show that the custom bus has high real-time communication and the communication process is stable and reliable.

关 键 词：嵌入式系统 FPGA 单片机 自定义并行总线 数据传输 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]