一种可节约RAM资源的准循环LDPC码的编码装置  

A Quasi-Cyclic LDPC Code Encoding Device That Can Save Ram Resources

作　　者：汪毅峰 潘涛 WANG Yifeng;PAN Tao(Nokia Shanghai Bell Co.,Ltd.,Nanjing Jiangsu 210037,China)

机构地区：[1]上海诺基亚贝尔股份有限公司,江苏南京210037

出　　处：《通信技术》2022年第5期652-655,共4页Communications Technology

摘　　要：低密度奇偶校验码(Low Density Parity Check Code,LDPC)是一种可接近香农容量限的分组码,具有纠错能力强、编码效率高、码率灵活可选等特点,但在编码方面,直接根据生成矩阵编码的运算量大,对硬件现场可编程门阵列(Field Programmable Gate Array,FPGA)计算和存储能力要求高。因此,提出一种以非0元素的位置表示法来代替原稀疏矩阵的值表示法,更经济地利用FPGA的随机存取存储器(Random Access Memory,RAM)资源,以移位寄存器方式实现LDPC码的编码方式,采取流水线结构减少FPGA硬件逻辑资源,通过矩阵变换,大大降低了RAM存储资源,节省了编码器的硬件资源。LDPC(Low Density Parity Check)code is a packet code that can approach the Shannon capacity limit,with strong error correction capability,high coding efficiency,and flexible code rate options.However,in terms of coding,direct coding based on the generation matrix is computationally intensive and requires high hardware FPGA(Field Programmable Gate Array)computation and storage capacity.This paper proposes a method to replace the value representation of the original sparse matrix with the position representation of non-zero elements,which makes more economical use of the RAM resources of FPGA,and implements the encoding method of LDPC code in the way of shift registers,and adopts the pipeline structure to reduce FPGA hardware logic resources,and through matrix transformation,thus greatly reduces the RAM storage resources and saves the hardware resources of the encoder.

关 键 词：随机存取存储器 准循环低密度奇偶校验码码 编码 稀疏矩阵 

分 类 号：TN929.53[电子电信—通信与信息系统]